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参数资料
| 型号： | 950908BGLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封装： | 0.240 INCH, 0.020 INCH PITCH, GREEN, MO-153, TSSOP-56 |
| 文件页数： | 5/24页 |
| 文件大小： | 305K |
| 代理商： | 950908BGLF-T |
13
Integrated
Circuit
Systems, Inc.
ICS950908
Preliminary Product Preview
0653A—07/26/04
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . . . . . . . 0°C to +70°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2VDD + 0.3
V
Input Low Voltage
VIL
VSS - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
mA
Input Low Current
IIL1
VIN = 0 V; Inputs with no pull-up resistors
-5
mA
Input Low Current
IIL2
VIN = 0 V; Inputs with pull-up resistors
-200
mA
Operating
CL = 0 pF; Select @ 66M
100
mA
Supply Current
CL = Full load
280
mA
IREF=2.32
20
mA
IREF= 5mA
37
mA
Input frequency
Fi
VDD = 3.3 V;
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
Cout
Out put pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Transition Time
1
Ttrans
To 1st crossing of target Freq.
3
mS
Settling Time
1
Ts
From 1st crossing to 1% target Freq.
3
mS
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target Freq.
3
mS
tPZH,tPZH
output enable delay (all outputs)
1
10
nS
tPLZ,tPZH
output disable delay (all outputs)
1
10
nS
1Guaranteed by design, not 100% tested in production.
Input Capacitance
1
Delay
IDD3.3OP
Power Down
Supply Current
IDD3.3PD
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