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参数资料
型号： 951402AGLFT
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟产生/分配
英文描述： 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封装： 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48
文件页数： 12/25页
文件大小： 320K
代理商： 951402AGLFT
2
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
Pin Description
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
2
FS0/REF0
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
3
FS1/REF1
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
4
FS2/REF2
I/O
Frequency select latch input pin / 14.318 MHz reference clock.
5
GNDREF
PWR
Ground pin for the REF outputs.
6
X1
IN
Crystal input, Nominally 14.318MHz.
7
X2
OUT
Crystal output, Nominally 14.318MHz
8
GND
PWR
Ground pin.
9
VDD
PWR
Power supply, nominal 3.3V
10
*VttPWR_GD/PD#
IN
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active high input. / Asynchronous active low input pin used to power
down the device into a low power state.
11
PCI66/33#_SEL
IN
Selects all PCI clock frequencies to be 33Mhz or 66Mhz. 0 = 33Mhz , 1
= 66Mhz
12
PCI_STOP#*
IN
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when
input low
13
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
14
FS3/PCICLK_F0
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
15
FS4/PCICLK_F1
I/O
Frequency select latch input pin / 3.3V PCI free running clock output.
16
PCICLK0
OUT
PCI clock output.
17
PCICLK1
OUT
PCI clock output.
18
GNDPCI
PWR
Ground pin for the PCI outputs
19
VDDPCI
PWR
Power supply for PCI clocks, nominal 3.3V
20
PCICLK2
OUT
PCI clock output.
21
PCICLK3
OUT
PCI clock output.
22
PCICLK4
OUT
PCI clock output.
23
PCICLK5
OUT
PCI clock output.
24
GNDPCI
PWR
Ground pin for the PCI outputs
25
GND48
PWR
Ground pin for the 48MHz outputs
26
24_48MHz/SEL24_48#MHz**
I/O
24/48MHz clock output / Latched select input for 24/48MHz output.
0=48MHz, 1 = 24MHz.
27
48MHz_1
OUT
48MHz clock output.
28
48MHz_0
OUT
48MHz clock output.
29
AVDD48
PWR
Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V
30
VDDAGP
PWR
Power supply for AGP clocks, nominal 3.3V
31
AGPCLK1
OUT
AGP clock output
32
AGPCLK0
OUT
AGP clock output
33
GNDAGP
PWR
Ground pin for the AGP outputs
34
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
35
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
36
AVDD
PWR
3.3V Analog Power pin for Core PLL
37
GND
PWR
Ground pin.
38
IREF
OUT
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
39
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. This clock is 180
degrees out of phase with the SDRAM clock.
40
CPUCLKT0
OUT
True clock of differential pair CPU outputs. This clock is in phase with
the SDRAM clock
41
GNDCPU
PWR
Ground pin for the CPU outputs
42
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
43
CPUCLKC1
OUT
Complementary clock of differential pair CPU outputs. This clock is 180
degrees out of phase with the SDRAM clock.
44
CPUCLKT1
OUT
True clock of differential pair CPU outputs. This clock is in phase with
the SDRAM clock
45
CPU_STOP#*
IN
Stops all CPUCLK besides the free running clocks
46
GNDSDR
PWR
Ground pin for the SDRAM outputs.
47
SDRAM_OUT
OUT
SDRAM seed clock output for external buffer
48
VDDSDR
PWR
Supply for SDRAM clocks, nominal 3.3V.
相关PDF资料
PDF描述
951402AGLF 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
951402AFLF 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
951402AFLFT 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
951411BGLF 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
951412AFLFT 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56
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