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参数资料
| 型号： | 951402AGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48 |
| 文件页数： | 14/25页 |
| 文件大小： | 320K |
| 代理商： | 951402AGLFT |
21
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
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