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参数资料
| 型号： | 951402AGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, GREEN, MO-153, TSSOP-48 |
| 文件页数： | 4/25页 |
| 文件大小： | 320K |
| 代理商： | 951402AGLFT |
12
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2C Table: Output Divider Control Register
Byte 16 Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
AGP Div3
RW
X
Bit 6
-
AGP Div2
RW
X
Bit 5
-
AGP Div1
RW
X
Bit 4
-
AGP Div0
AGP divider ratio can
be configured via
these 4 bits
individually
RW
See Table 2: Divider
Ratio Combination
Table
X
Bit 3
-
Reserved
RW
-
X
Bit 2
-
Reserved
RW
-
X
Bit 1
-
Reserved
RW
-
X
Bit 0
-
Reserved
RW
-
X
I
2C Table: Output Divider Control Register
Byte 17 Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
AGPINV
AGP Phase Invert
RW
Default
Inverse
X
Bit 6
-
Reserved
RW
-
X
Bit 5
-
SDINV
SDRAM
Phase Invert
RW
Default
Inverse
X
Bit 4
-
CPUINV
CPU Phase Invert
RW
Default
Inverse
X
Bit 3
-
PCIDiv3
RW
X
Bit 2
-
PCIDiv3
RW
X
Bit 1
-
PCIDiv3
RW
X
Bit 0
-
PCIDiv3
PCI divider ratio can
be configured via
these 4 bits
individually
RW
See Table 2 & 3:
Divider Ratio
Combination Table
X
I
2C Table: Group Skew Control Register
Byte 18 Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
CPUSkw3
RW
1
Bit 6
-
CPUSkw2
CPUT
Skew Control
RW
See 2-bit Skew
Control at table 4
0
Bit 5
-
SDSkw3
RW
0
Bit 4
-
SDSkw2
SDRAM
Skew Control
RW
See 2-bit Skew
Control at table 4
1
Bit 3
-
Reserved
RW
-
1
Bit 2
-
Reserved
RW
-
1
Bit 1
-
Reserved
RW
-
1
Bit 0
-
Reserved
RW
-
1
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