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参数资料
| 型号： | 95P04 |
| 厂商： | 意法半导体 |
| 英文描述： | SERIAL ACCESS SPI BUS 4K 512 x 8 EEPROM |
| 中文描述： | 串行访问SPI总线4K的512 × 8的EEPROM |
| 文件页数： | 2/16页 |
| 文件大小： | 151K |
| 代理商： | 95P04 |
Symbol
Parameter
Value
Unit
T
A
Ambient Operating Temperature
–40 to 85
°
C
T
STG
Storage Temperature
–65 to 150
°
C
T
LEAD
Lead Temperature, Soldering
(SO8 package)
(PSDIP8 package)
40 sec
10 sec
215
260
°
C
V
O
Output Voltage
–0.3 to V
CC
+0.6
V
V
I
Input Voltage
–0.3 to 6.5
V
V
CC
Supply Voltage
–0.3 to 6.5
V
V
ESD
Electrostatic Discharge Voltage (Human Body model)
(2)
4000
V
Electrostatic Discharge Voltage (Machine model)
(3)
500
V
Notes:
1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and
other relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500
)
3. EIAJ IC-121 (Condition C) (200pF, 0
)
Table 2. Absolute Maximum Ratings
(1)
SIGNALS DESCRIPTION
Serial Output (Q).
The output pin is used to trans-
fer data serially out of the ST95P04. Data is shifted
out on the falling edge of the serial clock.
Serial Input (D).
The input pin is used to transfer
data serially into the device. It receives instructions,
addresses, and data to be written. Input is latched
on the rising edge of the serial clock.
Serial Clock (C).
The serial clock provides the
timing of the serial interface. Instructions, ad-
dresses, or data present at the input pin are latched
on the rising edge of the clock input, while data on
the Q pin changes after the falling edge of the clock
input.
Chip Select (S).
This input is used to select the
ST95P04. The chip is selected by a high to low
transition on the S pin when C is at ’0’ state. At any
time, the chip is deselected by a low to high transi-
tion on the S pin when C is at ’0’ state. As soon as
the chip is deselected, the Q pin is at high imped-
ance state. This pin allows multiple ST95P04 to
share the same SPI bus. After power up, the chip
is at the deselect state. Transitions of S are ignored
when C is at ’1’ state.
D
VSS
C
HOLD
Q
W
S
VCC
AI01064B
ST95P04
1
2
3
4
8
7
6
5
Figure 2A. DIP Pin Connections
1
2
3
4
AI01065C
8
7
6
5
D
VSS
C
HOLD
Q
W
S
VCC
ST95P04
Figure 2B. SO Pin Connections
2/16
ST95P04
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