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参数资料
| 型号： | 9DB108BFLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件页数： | 10/16页 |
| 文件大小： | 144K |
| 代理商： | 9DB108BFLF-T |
3
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
0723G—12/02/08
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25
GND
PWR
Ground pin.
26
PD#
IN
Asynchronous active low input pin used to power down the
device. The internal clocks are disabled and the VCO and the
crystal are stopped.
27
SRC_STOP#
IN
Active low input to stop diff outputs.
28
HIGH_BW#
PWR
3.3V input for selecting PLL Band Width
0 = High, 1= Low
29
DIF_4#
OUT
0.7V differential complement clock outputs
30
DIF_4
OUT
0.7V differential true clock outputs
31
VDD
PWR
Power supply, nominal 3.3V
32
GND
PWR
Ground pin.
33
DIF_5#
OUT
0.7V differential complement clock outputs
34
DIF_5
OUT
0.7V differential true clock outputs
35
OE_5
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
36
OE_6
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
37
DIF_6#
OUT
0.7V differential complement clock outputs
38
DIF_6
OUT
0.7V differential true clock outputs
39
VDD
PWR
Power supply, nominal 3.3V
40
GND
PWR
Ground pin.
41
DIF_7#
OUT
0.7V differential complement clock outputs
42
DIF_7
OUT
0.7V differential true clock outputs
43
OE_4
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
44
OE_7
IN
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
45
LOCK
OUT
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
46
IREF
IN
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.
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参数描述 |
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| 9DB108BFLN | 制造商:Integrated Device Technology Inc 功能描述:PLL CLOCK BFFR SGL UP TO 200MHZ 48SSOP - Rail/Tube |
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| 9DB108BGLFT | 功能描述:时钟缓冲器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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| 9DB1200C | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM |
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