参数资料
型号: 9DB108YGT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封装: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
文件页数: 1/16页
文件大小: 144K
代理商: 9DB108YGT
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
0723G—12/02/08
Not
recommended
for
ne
w
designs
Pin Configuration
Recommended Application:
DB800 Intel Yellow Cover part with PCI-Express support.
Output Features:
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Key Specifications:
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
+/- 300ppm frequency accuracy on output clocks
Features/Benefits:
Supports tight ppm accuracy clocks for Serial-ATA
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
Supports undriven differential output pair in PD# and
SRC_STOP# for power management.
Eight Output Differential Buffer for PCI-Express
48-pin SSOP & TSSOP
SRC_DIV#
1
48 VDDA
VDD
2
47 GNDA
GND
3
46 IREF
SRC_IN
4
45 LOCK
SRC_IN#
5
44 OE_7
OE_0
6
43 OE_4
OE_3
742 DIF_7
DIF_0
841 DIF_7#
DIF_0#
940 GND
GND 10
39 VDD
VDD 11
38 DIF_6
DIF_1 12
37 DIF_6#
DIF_1# 13
36 OE_6
OE_1 14
35 OE_5
OE_2 15
34 DIF_5
DIF_2 16
33 DIF_5#
DIF_2# 17
32 GND
GND 18
31 VDD
VDD 19
30 DIF_4
DIF_3 20
29 DIF_4#
DIF_3# 21
28 HIGH_BW#
BYPASS#/PLL 22
27 SRC_STOP#
SCLK 23
26 PD#
SDATA 24
25 GND
ICS9DB108
相关PDF资料
PDF描述
9DB108YFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB108YFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB108YGLNT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB108YFLNT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB1200CGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64
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