- 您现在的位置：买卖IC网 > PDF目录25563 > 9DB108YGT (INTEGRATED DEVICE TECHNOLOGY INC) 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 PDF资料下载
参数资料
| 型号： | 9DB108YGT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件页数： | 12/16页 |
| 文件大小： | 144K |
| 代理商： | 9DB108YGT |
5
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
0723G—12/02/08
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
4.6
V
VDD_In
3.3V Logic Supply Voltage
4.6
V
VIL
Input Low Voltage
GND-0.5
V
VIH
Input High Voltage
VDD+0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
VDD + 0.3
V
Input Low Voltage
VIL
3.3 V +/-5%
GND - 0.3
0.8
V
Input High Current
IIH
VIN = VDD
-5
5
uA
IIL1
VIN = 0 V; Inputs with no pull-up
resistors
-5
uA
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
Operating Supply Current
IDD3.3OP
Full Active, CL = Full load;
250
mA
all diff pairs driven
60
mA
all differential pairs tri-stated
12
mA
Input Frequency
3
Fi
VDD = 3.3 V
80
100/133
166/200
220
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
1.5
5
pF
1
COUT
Output pin capacitance
6
pF
1
PLL Bandwidth when
PLL_BW=0
4MHz
1
PLL Bandwidth when
PLL_BW=1
2MHz
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up and after
input clock stabilization or de-
assertion of PD# to 1st clock
1ms
1,2
Modulation Frequency
Triangular Modulation
30
33
kHz
1
Tdrive_SRC_STOP#
DIF output enable after
SRC_Stop# de-assertion
10
ns
1,3
Tdrive_PD#
DIF output enable after
PD# de-assertion
300
us
1,3
Tfall
Fall time of PD# and
SRC_STOP#
5ns
1
Trise
Rise time of PD# and
SRC_STOP#
5ns
2
1Guaranteed by design and characterization, not 100% tested in production.
2See timing diagrams for timing requirements.
IDD3.3PD
3Time from deassertion until outputs are >200 mV
Input Capacitance
1
Input Low Current
Powerdown Current
PLL Bandwidth
BW
相关PDF资料 |
PDF描述 |
|---|---|
| 9DB108YFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB108YFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB108YGLNT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB108YFLNT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB1200CGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 12 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO64 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB1200BGLF | 制造商:Integrated Device Technology Inc 功能描述:PCIE GEN2 BUFFERS - Rail/Tube |
| 9DB1200C | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Twelve Output Differential Buffer for PCIe Gen1/Gen2, QPI, and FBDIMM |
| 9DB1200CGLF | 功能描述:时钟缓冲器 12 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB1200CGLFT | 功能描述:时钟缓冲器 12 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB1233 | 制造商:IDT 制造商全称:Integrated Device Technology 功能描述:Twelve Output Differential Buffer for PCIe Gen3 |
发布紧急采购，3分钟左右您将得到回复。