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| 型号： | 9DB801CFLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件页数： | 15/19页 |
| 文件大小： | 129K |
| 代理商： | 9DB801CFLFT |
IDTTM/ICSTM Eight Output Differential Buffer for PCI Express (50-200MHz)
9DB801C
REV E 01/27/11
ICS9DB801C
Eight Output Differential Buffer for PCI Express (50-200MHz)
5
Pin Description for OE_INV = 1
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
SRC_DIV#
INPUT
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
2
VDD
POWER
Power supply, nominal 3.3V
3
GND
POWER
Ground pin.
4
SRC_IN
INPUT
0.7 V Differential SRC TRUE input
5
SRC_IN#
INPUT
0.7 V Differential SRC COMPLEMENTARY input
6
OE0#
INPUT
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
7
OE3#
INPUT
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
8
DIF_0
OUTPUT 0.7V differential true clock outputs
9
DIF_0#
OUTPUT 0.7V differential complement clock outputs
10
GND
POWER
Ground pin.
11
VDD
POWER
Power supply, nominal 3.3V
12
DIF_1
OUTPUT 0.7V differential true clock outputs
13
DIF_1#
OUTPUT 0.7V differential complement clock outputs
14
OE1#
INPUT
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
15
OE2#
INPUT
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
16
DIF_2
OUTPUT 0.7V differential true clock outputs
17
DIF_2#
OUTPUT 0.7V differential complement clock outputs
18
GND
POWER
Ground pin.
19
VDD
POWER
Power supply, nominal 3.3V
20
DIF_3
OUTPUT 0.7V differential true clock outputs
21
DIF_3#
OUTPUT 0.7V differential complement clock outputs
22
BYPASS#/PLL
INPUT
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23
SCLK
INPUT
Clock pin of SMBus circuitry, 5V tolerant.
24
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
相关PDF资料 |
PDF描述 |
|---|---|
| 9DB801CGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DGILFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB803DFILF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9DB801CGLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB801CGLFT | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB803DFILF | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB803DFILFT | 功能描述:时钟缓冲器 RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9DB803DFLF | 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
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