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参数资料
型号： 9DB803DGILFT
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟及定时
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封装： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
文件页数： 21/21页
文件大小： 174K
代理商： 9DB803DGILFT
IDTTM/ICSTM
Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803D
REV K 05/09/11
ICS9DB803D
Eight Output Differential Buffer for PCIe for Gen 2
9
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA =Tambient; VDD = 3.3 V +/-5%; CL =2pF, RS=33, RP=49.9, RREF=475
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
1
3000
1
Voltage High
VHigh
660
850
1,2
Voltage Low
VLow
-150
150
1,2
Max Voltage
Vovs
1150
1
Min Voltage
Vuds
-300
1
Crossing Voltage (abs)
Vcross(abs)
250
550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
140
mV
1
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
125
ps
1
Fall Time Variation
d-tf
125
ps
1
Duty Cycle
dt3
Measurement from differential
wavefrom
45
55
%
1
tpdBYP
Bypass Mode, VT = 50%
2500
4500
ps
1
tpdPLL
PLL Mode VT = 50%
-250
250
ps
1
Skew, Output to Output
tsk3
VT = 50%
50
ps
1
PLL mode
50
ps
1,3
Additive Jitter in Bypass Mode
50
ps
1,3
PCIe Gen1 phase jitter
(Additive in Bypass Mode)
710
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter
(Additive in Bypass Mode)
00.1
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
(Additive in Bypass Mode)
0.3
0.5
ps
(rms)
1,4,5
PCIe Gen 1 phase jitter
40
86
ps
(pk2pk)
1,4,5
PCIe Gen 2 Low Band phase jitter
1.5
3
ps
(rms)
1,4,5
PCIe Gen 2 High Band phase jitter
2.7/
2.2
3.1
ps
(rms)
1,4,5,6
1Guaranteed by design and characterization, not 100% tested in production.
2 I
REF = VDD/(3xRR).
For RR = 475 (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
3 Measured from differential waveform
4 See http://www.pcisig.com for complete specs
5 Device driven by 932S421C or equivalent.
6 First number is High Bandwidth Mode, second number is Low Bandwidth Mode
Statistical measurement on single
ended signal using oscilloscope
math function.
mV
Measurement on single ended
signal using absolute value.
mV
tjphaseBYP
Jitter, Phase
tjphasePLL
Skew, Input to Output
Jitter, Cycle to cycle
tjcyc-cyc
相关PDF资料
PDF描述
9DB803DFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DFILF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DGT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
相关代理商/技术参数
参数描述
9DB803DGLF 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel
9DB803DGLFT 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel
9DB823BFLF 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel
9DB823BFLFT 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel
9DB823BGLF 功能描述:时钟缓冲器 8 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel
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