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| 型号： | 9DB833AGLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封装： | ROHS COMPLIANT, TSSOP-48 |
| 文件页数： | 14/18页 |
| 文件大小： | 226K |
| 代理商： | 9DB833AGLFT |
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
5
9DB833
REV C 052411
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DB833. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Electrical Characteristics–Clock Input Parameters
Electrical Characteristics–Current Consumption
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS N OTES
3.3V Core Supply Voltage
VDDA/R
4.6
V
1,2
3.3V Logic Supply Voltage
VDD
4.6
V
1,2
Input Low Voltage
VIL
GND-0.5
V
1
Input High Voltage
VIH
Except for SMBus interface
VDD+0.5V
V
1
Input High Voltage
VIHSM B
SMBus clock and data pins
5.5V
V
1
Storage Temperature
Ts
-65
150
°C1
Junction Temperature
Tj
125
°C
1
Input ESD protection
ESD prot
Human Body Model
2000
V
1
1Guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied nor guaranteed.
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage - DIF_IN
V
IHD IF
Differential inputs
(single-ended measurement)
600
800
1150
mV
1
Input Low Voltage - DIF_IN
VIL DIF
Differential inputs
(single-ended measurement)
VSS - 300
0300
mV
1
Input C ommon Mode Voltage
- DIF_IN
VCOM
Common Mode Input Voltage
300
1000
mV
1
Input Amplitude - D IF_IN
VSWING
Peak to Peak value
300
1450
mV
1
Input Slew Rate - DIF_IN
dv/dt
Measured differentially
0.4
8
V/ns
1,2
Input Leakage Current
I
IN
V
IN = VDD , VIN = GND
-5
5
uA
1
Input Duty Cycle
dtin
Measurement from differential wavefrom
45
55
%
1
Input Jitter - Cycle to Cycle
JDIFIn
Differential Measurement
0
125
ps
1
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
TA = TCOM or TI ND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Operating Supply Current
IDD3.3 OP
All outputs active @100MHz, CL = Full load;
170
200
mA
1
IDD3 .3PD
All diff pairs driven
53
60
mA
1
I
D D3.3 PDZ
All differential pairs tri-stated
3
6
mA
1
1Guaranteed by design and characterization, not 100% tested in production.
Pow erdown Current
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