参数资料
型号: 9DB833AGLFT
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 时钟及定时
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封装: ROHS COMPLIANT, TSSOP-48
文件页数: 3/18页
文件大小: 226K
代理商: 9DB833AGLFT
9DB833
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
IDT
EIGHT OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN3
11
9DB833
REV C 052411
General SMBus Serial Interface Information
How to Write
Controller (host) sends a start bit
Controller (host) sends the write address
*
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) sends the byte count = X
IDT clock will acknowledge
Controller (host) starts sending Byte N through Byte
N+X-1
IDT clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
* Assuming SMB_ADR_tri is at mid-level
How to Read
Controller (host) will send a start bit
Controller (host) sends the write address
*
IDT clock will acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
*
IDT clock will acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte N+X-1
IDT clock sends Byte 0 through Byte X (if X(H) was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
IDT (Slave/Receiver)
TstarT bit
Slave Address
WR
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
X
B
y
te
ACK
O
Byte N + X - 1
ACK
PstoP bit
Read Address
Write Address
DD(H)
DC(H)
Index Block Read Operation
Controller (Host)
IDT (Slave/Receiver)
TstarT bit
Slave Address
WR
WRite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address
RD
ReaD
ACK
Data Byte Count=X
ACK
X
By
te
Beginning Byte N
ACK
O
Byte N + X - 1
N
Not acknowledge
PstoP bit
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9DB833AGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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