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参数资料
| 型号： | 9FG104DFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封装： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-28 |
| 文件页数： | 12/17页 |
| 文件大小： | 161K |
| 代理商： | 9FG104DFLF |
IDT
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
4
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = TAM BIENT; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
V
DD + 0.3
V1
Input Low Voltage
VIL
3.3 V +/-5%
V
SS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Full Active, CL = Full load;
f = 400 MHz
125
150
mA
1
Full Active, CL = Full load;
f = 100 MHz
110
125
mA
1
All outputs stopped driven
106
120
mA
1
All outputs stopped Hi-Z
48
60
mA
1
SEL14M_25M# = 0
22.5
25.00
27.5
MHz
3
SEL14M_25M# = 1
12.886 14.31818
15.75
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
1.5
5
pF
1
COUT
Output pin capacitance
6
pF
1
TSTABcom
From VDD Power-Up to 1st
clock (Commercial)
1.8
ms
1,2
TSTABind
From VDD Power-Up to 1st
clock (Industrial)
1.8
ms
1,2
Modulation Frequency
fMOD
SEL14M_25M# = 0
32.541
kHz
1,3,4
Modulation Frequency
fMOD
SEL14M_25M# = 1
32.467
kHz
1,3,4
DIF output enable
tDIFOE
DIF output enable after
DIF_Stop# de-assertion
15
ns
1
Input Rise and Fall times
tR/tF
20% to 80% of VDD
5
ns
1
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
4 These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency
will scale these frequencies accordingly. The output frequecy selected by the FS inputs will also scale.
For example, 27MHz input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 =
108MHz.
3 Input frequency should be measured at the REF pin and tuned to 0 PPM to meet
ppm frequency accuracy on PLL outputs.
Input/Output
Capacitance
1
Fi
Input Frequency
3
Clk Stabilization
1,2
Input Low Current
IDD3.3STOP
IDD3.3OP
Operating Supply Current
Symbol
Parameter
Min
Max
Units
VDDxx
3.3V Supply Voltage
4.6
V
Ts
Storage Temperature
-65
150
°C
Tambient Ambient Operating Temp(Commerical Grade)
0+70
°C
Tambient
Ambient Operating Temp(Industrial Grade)
-40
+85
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protectionhuman body model
2000
V
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9FG104DFLFT | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG104DGILF | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG104DGILFT | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG104DGLF | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG104DG-LF | 制造商:Integrated Device Technology Inc 功能描述:PROGRAMMABLE PLL FREQ TIMING GENERATOR SGL 28TSSOP - Rail/Tube |
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