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参数资料
| 型号： | 9FG108DFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件页数： | 12/18页 |
| 文件大小： | 166K |
| 代理商： | 9FG108DFLF |
IDTTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1542E 12/16/10
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
3
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
XIN /C LKIN
IN
C rystal inpu t or R e feren ce C lock in put
2
X2
OU T
C rystal outp ut, N om inally 14 .318 MH z
3
VD D
PWR
Pow e r supp ly, nom inal 3.3 V
4
GN D
PWR
Groun d pin.
5
R EFOU T
OU T
R e fere nce C lock o utput
6
vFS2
IN
Freq uency se lect pin . This pin has a n internal 1 20k pu ll dow n resistor
7vOE_7
IN
Active hig h inp ut for enab ling o utpu t 7. This p in ha s a 120 kohm pull do w n.
0 = tri-sta te ou tputs, 1 = ena ble o utpu ts
8
D IF_ 7
OU T
0 .7V differe ntial true clock o utpu t
9
D IF_ 7#
OU T
0 .7V differe ntial C o mplem enta ry clock ou tput
1 0
VD D
PWR
Pow e r supp ly, nom inal 3.3 V
1 1
D IF_ 6
OU T
0 .7V differe ntial true clock o utpu t
1 2
D IF_ 6#
OU T
0 .7V differe ntial C o mplem enta ry clock ou tput
13
^OE_6
IN
Active hig h inp ut for enab ling o utpu t 6. This p in ha s a n inte rna l 120ko hm p ull up .
0 = tri-sta te ou tputs, 1 = ena ble o utpu ts
1 4
VD D
PWR
Pow e r supp ly, nom inal 3.3 V
1 5
GN D
PWR
Groun d pin.
16
^OE_5
IN
Active hig h inp ut for enab ling o utpu t 5. This p in ha s a n inte rna l 120ko hm p ull up .
0 = tri-sta te ou tputs, 1 = ena ble o utpu ts
1 7
D IF_ 5
OU T
0 .7V differe ntial true clock o utpu t
1 8
D IF_ 5#
OU T
0 .7V differe ntial C o mplem enta ry clock ou tput
1 9
VD D
PWR
Pow e r supp ly, nom inal 3.3 V
2 0
D IF_ 4
OU T
0 .7V differe ntial true clock o utpu t
2 1
D IF_ 4#
OU T
0 .7V differe ntial C o mplem enta ry clock ou tput
22
vOE_4
IN
Active hig h inp ut for enab ling o utpu t 4. This p in as an internal 1 20koh m pu ll dow n.
0 = tri-sta te ou tputs, 1 = ena ble o utpu ts
2 3
SD ATA
I/O
D a ta pin fo r SMBus circuitry, 3.3V tolerant.
2 4
SC LK
IN
C lo ck pin of SMBus circu itry, 5V tole rant.
Note:
^ indic ates internal 120K pull up
v indic ates internal 120K pull down
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相关代理商/技术参数 |
参数描述 |
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| 9FG108DFLFT | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG108DGILF | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG108DGI-LF | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Single 48-Pin TSSOP Tube |
| 9FG108DGILFT | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG108DGLF | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
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