- 您现在的位置：买卖IC网 > PDF目录25566 > 9FG108DFLF (INTEGRATED DEVICE TECHNOLOGY INC) 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF资料下载
参数资料
| 型号： | 9FG108DFLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封装： | 0.300 INCH, ROHS COMPLIANT, MO-118, SSOP-48 |
| 文件页数： | 4/18页 |
| 文件大小： | 166K |
| 代理商： | 9FG108DFLF |
IDTTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1542E 12/16/10
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
12
SMBus Table: PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL N Div8
N Divider Prog bit 8
RW
X
Bit 6
PLL N Div9
N Divider Prog bit 9
RW
X
Bit 5
PLL M Div5
RW
X
Bit 4
PLL M Div4
RW
X
Bit 3
PLL M Div3
RW
X
Bit 2
PLL M Div2
RW
X
Bit 1
PLL M Div1
RW
X
Bit 0
PLL M Div0
RW
X
SMBus Table: PLL Frequency Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL N Div7
RW
X
Bit 6
PLL N Div6
RW
X
Bit 5
PLL N Div5
RW
X
Bit 4
PLL N Div4
RW
X
Bit 3
PLL N Div3
RW
X
Bit 2
PLL N Div2
RW
X
Bit 1
PLL N Div1
RW
X
Bit 0
PLL N Div0
RW
X
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
PLL SSP7
RW
X
Bit 6
PLL SSP6
RW
X
Bit 5
PLL SSP5
RW
X
Bit 4
PLL SSP4
RW
X
Bit 3
PLL SSP3
RW
X
Bit 2
PLL SSP2
RW
X
Bit 1
PLL SSP1
RW
X
Bit 0
PLL SSP0
RW
X
SMBus Table: PLL Spread Spectrum Control Register
Pin #
Name
Control Function
Type
0
1
Default
Bit 7
0
Bit 6
PLL SSP14
RW
X
Bit 5
PLL SSP13
RW
X
Bit 4
PLL SSP12
RW
X
Bit 3
PLL SSP11
RW
X
Bit 2
PLL SSP10
RW
X
Bit 1
PLL SSP9
RW
X
Bit 0
PLL SSP8
RW
X
Byte 10
-
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
M Divider Programming
bit (5:0)
-
Byte 11
-
The decimal
representation of M and
N Divider in Byte 11 and
12 will configure the PLL
VCO frequency.
Default at power up =
latch-in or Byte 0 Rom
table. VCO Frequency
= fXTAL x [NDiv(9:0)+8]
/ [MDiv(5:0)+2]
-
Byte 12
-
N Divider Programming
Byte11 bit(7:0) and
Byte10 bit(7:6)
-
Spread Spectrum
Programming bit(7:0)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
Byte 13
-
Reserved
-
Spread Spectrum
Programming bit(14:8)
These Spread
Spectrum bits in
Byte 13 and 14 will
program the spread
pecentage of PLL
-
相关PDF资料 |
PDF描述 |
|---|---|
| 9FG108DFILF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG108DGLFT | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG108DGLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 9FG1200DF-1LFT | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 9FG1200DG-1LF | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 9FG108DFLFT | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG108DGILF | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG108DGI-LF | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Single 48-Pin TSSOP Tube |
| 9FG108DGILFT | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
| 9FG108DGLF | 功能描述:时钟合成器/抖动清除器 PCIE GEN2 SYNTHESIZER RoHS:否 制造商:Skyworks Solutions, Inc. 输出端数量: 输出电平: 最大输出频率: 输入电平: 最大输入频率:6.1 GHz 电源电压-最大:3.3 V 电源电压-最小:2.7 V 封装 / 箱体:TSSOP-28 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。