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参数资料
| 型号： | 9FG1201HGLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件页数： | 22/23页 |
| 文件大小： | 268K |
| 代理商： | 9FG1201HGLF |
IDTTM/ICSTM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
8
General SMBus serial interface information for the ICS9FG1201H
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D0
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D0
(h)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D1
(h)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
PstoP bit
X
By
te
Index Block Write Operation
Slave Address D0(h)*
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X
By
te
ACK
Data Byte Count = X
ACK
Slave Address D1(h)*
Index Block Read Operation
Slave Address D0(h)*
Beginning Byte = N
ACK
* Note: See SMBus Address Mapping (page 7), for programming SMBus Read/Write Address
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 9FG1201HGLFT | 功能描述:时钟缓冲器 12 Output PCIe Gearng Buffer RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9FG1900AK-1LF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9FG1900AK-1LF LOGIC AND TIMING MISC - Trays 制造商:Integrated Device Technology Inc 功能描述:IDT 9FG1900AK-1LF Logic and Timing Misc |
| 9FG1900BK-1LF | 功能描述:时钟缓冲器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9FG1900BK-1LFT | 功能描述:时钟缓冲器 PCIE BUFFER RoHS:否 制造商:Texas Instruments 输出端数量:5 最大输入频率:40 MHz 传播延迟（最大值）: 电源电压-最大:3.45 V 电源电压-最小:2.375 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LLP-24 封装:Reel |
| 9FG1901CKLF | 制造商:Integrated Device Technology Inc 功能描述:PLL Frequency Generator Dual 72-Pin VFQFPN EP Tray 制造商:Integrated Device Technology Inc 功能描述:PCIE BUFFER |
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