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参数资料
| 型号： | 9FG1201HGLF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 400 MHz, OTHER CLOCK GENERATOR, PDSO56 |
| 封装： | 6.10 MM, 0.50 PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件页数： | 8/23页 |
| 文件大小： | 268K |
| 代理商： | 9FG1201HGLF |
IDTTM/ICSTM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
16
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2
, RP=49.9, ΙREF = 475
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
1
VO = Vx
3000
1
Voltage High
VHigh
660
850
1,3
Voltage Low
VLow
-150
150
1,3
Max Voltage
Vovs
1150
1
Min Voltage
Vuds
-300
1
Crossing Voltage (abs)
Vcross(abs
)
250
550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all
edges
140
mV
1
Long Accuracy
ppmsee Tperiod min-max values
-300
300
ppm1,2
400MHz nominal
2.4993
2.5008
ns
2
400MHz spread
2.4993
2.5133
ns
2
333.33MHz nominal
2.9991
3.0009
ns
2
333.33MHz spread
2.9991
3.016
ns
2
266.66MHz nominal
3.7489
3.7511
ns
2
266.66MHz spread
3.7489
3.77
ns
2
200MHz nominal
4.9985
5.0015
ns
2
200MHz spread
4.9985
5.0266
ns
2
166.66MHz nominal
5.9982
6.0018
ns
2
166.66MHz spread
5.9982
6.0320
ns
2
133.33MHz nominal
7.4978
7.5023
ns
2
133.33MHz spread
7.4978
7.5400
ns
2
100.00MHz nominal
9.9970
10.0030
ns
2
100.00MHz spread
9.9970
10.0533
ns
2
400MHz nominal/spread
2.4143
ns
1,2
333.33MHz nominal/spread
2.9141
ns
1,2
266.66MHz nominal/spread
3.6639
ns
1,2
200MHz nominal/spread
4.8735
ns
1,2
166.66MHz nominal/spread
5.8732
ns
1,2
133.33MHz nominal/spread
7.3728
ns
1,2
100.00MHz nominal/spread
9.8720
ns
1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
125
ps
1
Fall Time Variation
d-tf
125
ps
1
Duty Cycle
dt3
Measurement from differential
wavefrom
45
55
%
1
tJCYC-CYC
PLL mode,
from differential wavefrom
50
ps
1,4,5
tJBYP
Bypass mode as additive jitter
50
ps
1,4
Notes:
1.Guaranteed by design and characterization, not 100% tested in production.
3.IREF = VDD/(3xRR). For RR = 475
(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
5. Measured from differential cross-point to differential cross-point
6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
Jitter, Cycle to cycle
2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410B accuracy requirements
Absolute min period
Tabsmin
Average period
Tperiod
Measurement on single ended
signal using absolute value.
mV
Statistical measurement on
single ended signal using
oscilloscope math function.
mV
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