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参数资料
| 型号： | 9LPRS480YKLFT |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | PROC SPECIFIC CLOCK GENERATOR, PQCC64 |
| 封装： | ROHS COMPLIANT, PLASTIC, MLF-64 |
| 文件页数： | 9/25页 |
| 文件大小： | 249K |
| 代理商： | 9LPRS480YKLFT |
17
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
1391D—02/02/09
SMBus Table: Latched Input Readback Output Enable Control Register
Byte
0
Name
Description
Type
0
1
Default
Bit 7
SEL_HTT66 readback
Hypertransport Select
R
100MHz Differential HTT
clock
66 MHz 3.3V Single-
ended HTT clock
Latch
Bit 6
SEL_SATA readback
SATA Select
R
SRC6/SATA pair is SRC
SS capable output
SRC6/SATA pair is
SATA non-spread
output
Latch
Bit 5
REF0_OE
Output Enable
RW
Hi-Z
Enabled
1
Bit 4
REF1_OE
Output Enable
RW
Hi-Z
Enabled
1
Bit 3
REF2_OE
Output Enable
RW
Hi-Z
Enabled
1
Bit 2
0
Bit 1
48MHz_0_OE
Output Enable
RW
Low
Enabled
1
Bit 0
SS_Enable
Spread Spectrum Enable
(CPU, SRC, SB_SRC,
ATIG)
RW
Spread Off
Spread On
0
SMBus Table:Output Enable Control Register
Byte
1
Name
Control Function
Type
0
1
Default
Bit 7
SRC7/27MHz_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 6
SRC6/SATA_OE Enable
Output Enable
RW
Low/Low
Enabled
1
Bit 5
0
Bit 4
SRC4_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 3
SRC3_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 2
SRC2_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 1
SRC1_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 0
SRC0_OE
Output Enable
RW
Low/Low
Enabled
1
SMBus Table: Output Enable and 48MHz Slew Rate Control Register
Byte
2
Name
Control Function
Type
0
1
Default
Bit 7
SB_SRC1_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 6
SB_SRC0_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 5
1
Bit 4
1
Bit 3
ATIG1_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 2
ATIG0_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 1
27MHz_SS_Enable
Spread Spectrum Enable
27MHz_SS
RW
Spread Off
Spread On
0
Bit 0
Reserved
RW
-
X
SMBus Table: CPU/HTT Frequency Control Register
Byte
3
Name
Control Function
Type
0
1
Default
Bit 7
CPU0_OE
Output enable
RW
Low/Low
Enable
1
Bit 6
SEL_27 readback
SRC7/27MHz Select
R
SRC7 Output
27MHz Output
Latch
Bit 5
1
Bit 4
HTT/66MHz_OE
Output Enable
RW
Low/Low
Enabled
1
Bit 3
CPU_FS3
CPU Frequency Select
RW
0
Bit 2
CPU_FS2
CPU Frequency Select
RW
1
Bit 1
CPU_FS1
CPU Frequency Select
RW
1
Bit 0
CPU_FS0
CPU Frequency Select LSB
RW
1
48MHz_0_Slew Rate
RW
See CPU/HTT/SRC/ATIG Frequency Select
Table
Default value corresponds to 200MHz.
Note that the HTT frequency tracks the CPU
frequency.
These bits program the slew rate of the single
ended outputs. The maximum slew rate is
1.9V/ns and the minimum slew rate is 1.1V/ns.
The slew rate selection is as follows:
11 = 1.9V/ns
10 = 1.6V/ns
01 = 1.1V/ns
00 = tristated
Slew Rate Control
Reserved
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