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参数资料
型号： 9P035YFLF-T
厂商： INTEGRATED DEVICE TECHNOLOGY INC
元件分类： 时钟及定时
英文描述： 9P SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8
封装： 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-8
文件页数： 12/13页
文件大小： 191K
代理商： 9P035YFLF-T
IDTTM/ICSTM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
REV H
12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
8
Timing Requirements
Switching Characteristics
3
Notes:
1.
Refers to transition on noninverting output in PLL bypass mode.
2.
While the pulse skew is almost constant over frequency, the duty cycle error increases at
higher frequencies. This is due to the formula: duty cycle=twH/tc, were the cycle (tc)
decreases as the frequency goes up.
3.
Switching characteristics guaranteed for application frequency range.
4.
Static phase offset shifted by design.
TA = 0 - =70°C; Supply Voltage AVDD, VDD = 2.5 V +/- 0.2V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Max clock frequency
freqop
2.5V+0.2V @ 25
oC
45
600
MHz
Application Frequency
Range
freqApp
2.5V+0.2V @ 25
oC
95
233
MHz
Input clock duty cycle
dtin
40
60
%
CLK stabilization
TSTAB
15
s
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
Low-to high level
propagation delay time
tPLH
1
BUF_IN to any output
3.5
ns
High-to low level propagation
delay time
tPLL
1
BUF_IN to any output
3.5
ns
Period jitter
Tjit (per)
100MHz to 200MHz
-30
30
ps
Half-period jitter
t(jit_hper)
100MHz to 200MHz
-100
100
ps
Input clock slew rate
tsl(i)
14
V/ns
Output clock slew rate
tsl(o)
12
V/ns
Cycle to Cycle Jitter
1
Tcyc-Tcyc
100MHz to 200MHz
-50
50
ps
Static Phase Offset
t(static phase offset)
4
-50
0
50
ps
Output to Output Skew
Tskew
40
ps
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