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| 型号： | 9P035YFLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9P SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 0.209 INCH, ROHS COMPLIANT, MO-150, SSOP-8 |
| 文件页数： | 8/13页 |
| 文件大小： | 191K |
| 代理商： | 9P035YFLF-T |
IDTTM/ICSTM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
REV H
12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
4
Notes:
1.
Unused inputs must be held high or low to prevent them from floating.
2.
DC input signal voltage specifies the allowable DC execution of differential input.
3.
Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required
for switching, where VTR is the true input level and VCP is the complementary input
level.
4.
Differential cross-point voltage is expected to track variations of VDD and is the voltage
at which the differential signal must be crossing.
Recommended Operating Condition (see note1)
TA = 0 - 70°C; Supply Voltage AVDD, VDD = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage
VDDQ, AVDD
1.7
1.8
1.9
V
Low level input voltage
VIL
CLK_INT, CLK_INC, FB_IN
0.35 x VDD
V
High level input voltage
VIH
CLK_INT, CLK_INC, FB_IN
0.65 x VDD
V
DC input signal voltage (note 2)
VIN
-0.3
VDD + 0.3
V
DC input signal voltage swing
VIN-Diff
CLK_INT, CLK_INC
GND - 0.3
1.5
VDD + 0.3
V
DC - CLK_INT, CLK_INC,
FB_IN
0.3
VDD + 0.4
V
AC - CLK_INT, CLK_INC,
FB_IN
0.6
VDD + 0.4
V
Output differential cross-voltage
(note 4)
VOX
VDD / 2 - 0.1
VDD / 2 + 0.1
V
Input differential cross-voltage
(note 4)
VIX
VDD/2 - 0.15
VDD/2 VDD / 2 + 0.15
V
High level output current
IOH
-9
mA
Low level output current
IOL
9mA
High Impedance
Output Current
IOZ
VDD=1.9V, VOUT=VDD or GND
±10
mA
Operating free-air temperature
TA
070
°C
Differential input signal voltage
(note 3)
VID
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