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| 型号： | 9P035YGLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9P SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-8 |
| 文件页数： | 13/13页 |
| 文件大小： | 191K |
| 代理商： | 9P035YGLF-T |
IDTTM/ICSTM
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
ICS9P935
REV H
12/1/08
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
9
1.
The IDT clock generator is a slave/receiver, I
2C component. It can read back the data stored in the latches for verification.
Read-Back will support SMBus block read protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must
be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred.
The Command code and Byte count shown above must be sent, The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
Notes:
General I
2C serial interface information for the ICS9P935
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
ICS clock will
acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D5
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
P
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
stoP bit
X
By
te
Index Block Write Operation
Slave Address D4(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
TstarT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
PstoP bit
ICS (Slave/Receiver)
Controller (Host)
X
Byt
e
ACK
Data Byte Count = X
ACK
Slave Address D5(H)
Index Block Read Operation
Slave Address D4(H)
Beginning Byte = N
ACK
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