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| 型号： | 9P035YGLF-T |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | 时钟及定时 |
| 英文描述： | 9P SERIES, PLL BASED CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO8 |
| 封装： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-8 |
| 文件页数： | 5/13页 |
| 文件大小： | 191K |
| 代理商： | 9P035YGLF-T |
ICS9P935
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
13
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
408-284-6578
pcclockhelp@idt.com
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Revision History
Rev.
Issue Date Description
Page #
A
2/8/2007
Final Release.
-
B
6/4/2007
Fixed various typos.
-
C
6/14/2007
Added TSSOP Ordering Information.
12
D
6/20/2007
1. Updated Output Features: Max Frequency Supported.
2. Updated DDRI/DDRII Max Clock Frequency.
1
5, 8
E
8/16/2007
1. Updated Supply Voltage.
2. Updated Input High/Low Current Max.
3
F
9/5/2007
Updated Electrical Specifications.
3-5
G
11/19/2007 Updated Serial Interface Information.
9
H
12/1/2008
Updated Pin Description.
2
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| 9P935AFLFT | 9P SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
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