参数资料
| 型号： | A14100A-1RQ208I |
| 厂商： | Microsemi SoC |
| 文件页数： | 4/90页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 10K GATES 208-PQFP |
| 标准包装： | 24 |
| 系列： | ACT™ 3 |
| LAB/CLB数： | 1377 |
| 输入/输出数： | 175 |
| 门数： | 10000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 208-BFQFP 裸露焊盘 |
| 供应商设备封装： | 208-RQFP（28x28） |
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Detailed Specifications
2- 4
R e v ision 3
The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into
the array. This allows the output register to be used in high-speed state machine applications. Side I/O
modules have a dedicated output segment for Y extending into the routing channels above and below
(similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained
in detail in the routing section).
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four
signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only
during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN
(global input enable), and SLEW (individual slew selection). See Figure 2-5.
Special I/Os
The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during
programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent
special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change
once the device has been programmed. The permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input
buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is
determined by the I/O macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks
and two general purpose routed networks. The high-performance networks function up to 200 MHz,
while the general purpose routed networks function up to 150 MHz.
Figure 2-5
Function Diagram for I/O Pad Driver
PAD
OE
SLEW
DATAOUT
DATAIN
IEN
INEN
OUTEN
相关PDF资料 |
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