参数资料
| 型号： | A1460A-1CQ196C |
| 厂商： | Microsemi SoC |
| 文件页数： | 4/90页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 6K GATES 196-CQFP |
| 标准包装： | 1 |
| 系列： | ACT™ 3 |
| LAB/CLB数： | 848 |
| 输入/输出数： | 168 |
| 门数： | 6000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 196-BCQFP，带拉杆 |
| 供应商设备封装： | 196-CQFP（63.5x63.5） |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页
Detailed Specifications
2- 4
R e v ision 3
The I/O module output Y is used to bring Pad signals into the array or to feed the output register back into
the array. This allows the output register to be used in high-speed state machine applications. Side I/O
modules have a dedicated output segment for Y extending into the routing channels above and below
(similar to logic modules). Top/Bottom I/O modules have no dedicated output segment. Signals coming
into the chip from the top or bottom are routed using F-fuses and LVTs (F-fuses and LVTs are explained
in detail in the routing section).
I/O Pad Drivers
All pad drivers are capable of being tristate. Each buffer connects to an associated I/O module with four
signals: OE (Output Enable), IE (Input Enable), DataOut, and DataIn. Certain special signals used only
during programming and test also connect to the pad drivers: OUTEN (global output enable), INEN
(global input enable), and SLEW (individual slew selection). See Figure 2-5.
Special I/Os
The special I/Os are of two types: temporary and permanent. Temporary special I/Os are used during
programming and testing. They function as normal I/Os when the MODE pin is inactive. Permanent
special I/Os are user programmed as either normal I/Os or special I/Os. Their function does not change
once the device has been programmed. The permanent special I/Os consist of the array clock input
buffers (CLKA and CLKB), the hard-wired array clock input buffer (HCLK), the hard-wired I/O clock input
buffer (IOCLK), and the hard-wired I/O register preset/clear input buffer (IOPCL). Their function is
determined by the I/O macros selected.
Clock Networks
The ACT 3 architecture contains four clock networks: two high-performance dedicated clock networks
and two general purpose routed networks. The high-performance networks function up to 200 MHz,
while the general purpose routed networks function up to 150 MHz.
Figure 2-5
Function Diagram for I/O Pad Driver
PAD
OE
SLEW
DATAOUT
DATAIN
IEN
INEN
OUTEN
相关PDF资料 |
PDF描述 |
|---|---|
| ASC50DRTN-S734 | CONN EDGECARD 100PS DIP .100 SLD |
| EP2SGX60DF780I4N | IC STRATIX II GX 60K 780-FBGA |
| 24LC01BHT-I/ST | IC EEPROM 1KBIT 400KHZ 8TSSOP |
| EP2SGX60DF780C3N | IC STRATIX II GX 60K 780-FBGA |
| ASC50DRTH-S734 | CONN EDGECARD 100PS DIP .100 SLD |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A1460A-1CQ196M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 196-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um Technology 5V 196-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 6K GATES 848 CELLS 125MHZ 0.8UM 5V 196CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 6K GATES 196-CQFP |
| A1460A-1CQ256B | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
| A1460A-1CQ256C | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
| A1460A-1CQ256E | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
| A1460A-1CQ256M | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
发布紧急采购，3分钟左右您将得到回复。