参数资料
| 型号： | A1460A-1CQ196C |
| 厂商： | Microsemi SoC |
| 文件页数： | 8/90页 |
| 文件大小： | 0K |
| 描述： | IC FPGA 6K GATES 196-CQFP |
| 标准包装： | 1 |
| 系列： | ACT™ 3 |
| LAB/CLB数： | 848 |
| 输入/输出数： | 168 |
| 门数： | 6000 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 安装类型： | 表面贴装 |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 196-BCQFP，带拉杆 |
| 供应商设备封装： | 196-CQFP（63.5x63.5） |
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Detailed Specifications
2- 8
R e v ision 3
Module Output Connections
Module outputs have dedicated output segments. Output segments extend vertically two channels above
and two channels below, except at the top or bottom of the array. Output segments twist, as shown in
Figure 10, so that only four vertical tracks are required.
LVT Connections
Outputs may also connect to nondedicated segments called Long Vertical Tracks (LVTs). Each module
pair in the array shares four LVTs that span the length of the column. Any module in the column pair can
connect to one of the LVTs in the column using an FF connection. The FF connection uses antifuses
connected directly to the driver stage of the module output, bypassing the isolation transistor. FF
antifuses are programmed at a higher current level than HF, VF, or XF antifuses to produce a lower
resistance value.
Antifuse Connections
In general every intersection of a vertical segment and a horizontal segment contains an unprogrammed
antifuse (XF-type). One exception is in the case of the clock networks.
Clock Connections
To minimize loading on the clock networks, a subset of inputs has antifuses on the clock tracks. Only a
few of the C-module and S-module inputs can be connected to the clock networks. To further reduce
loading on the clock network, only a subset of the horizontal routing tracks can connect to the clock
inputs of the S-module.
Programming and Test Circuits
The array of logic and I/O modules is surrounded by test and programming circuits controlled by the
temporary special I/O pins MODE, SDI, and DCLK. The function of these pins is similar to all ACT family
devices. The ACT 3 family also includes support for two Actionprobe circuits, allowing complete
observability of any logic or I/O module in the array using the temporary special I/O pins, PRA and PRB.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| A1460A-1CQ196M | 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um (CMOS) Technology 5V 196-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 Family 6K Gates 848 Cells 125MHz 0.8um Technology 5V 196-Pin CQFP 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 6K GATES 848 CELLS 125MHZ 0.8UM 5V 196CQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 6K GATES 196-CQFP |
| A1460A-1CQ256B | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
| A1460A-1CQ256C | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
| A1460A-1CQ256E | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
| A1460A-1CQ256M | 制造商:ACTEL 制造商全称:Actel Corporation 功能描述:HiRel FPGAs |
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