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参数资料
| 型号： | A28F400BR-T |
| 英文描述： | 4-MBIT (256K X 16. 512K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| 中文描述： | 4兆位（256 × 16。为512k × 8）SmartVoltage启动块闪存系列 |
| 文件页数： | 15/36页 |
| 文件大小： | 457K |
| 代理商： | A28F400BR-T |
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Erase Confirm (D0H)
A28F400BR-T/B
15
ADVANCE INFORMATION
If the previous command was an Erase Setup
command, then the CUI will enable the WSM to
erase, at the same time closing the address and
data latches, and respond only to the Read Status
Register and Erase Suspend commands. While the
WSM is executing, the device will output Status
Register data when OE# is toggled low. Status
Register data can only be updated by toggling
either OE# or CE# low.
Erase Suspend (B0H)
This command is only valid while the WSM is
executing an erase operation, and therefore will
only be responded to during an erase operation.
After this command has been executed, the CUI will
set an output that directs the WSM to suspend
erase operations, and then respond only to Read
Status Register or to
commands. Once the WSM has reached the
Suspend state, it will set an output into the CUI
which allows the CUI to respond to the Read Array,
Read Status Register, and Erase Resume
commands. In this mode, the CUI will not respond
to any other commands. The WSM will also set the
WSM Status bit to a
“1.” The WSM will continue to
run, idling in the SUSPEND state, regardless of the
state of all input control pins except RP#, which will
immediately shut down the WSM and the remainder
of the chip, if it is made active. During a suspend
operation, the data and address latches will remain
closed, but the address pads are able to drive the
address into the read path.
the
Erase
Resume
Erase Resume (D0H)
This command will cause the CUI to clear the
Suspend state and clear the WSM Status Bit to a
“0,” but only if an Erase Suspend command was
previously issued. Erase Resume will not have any
effect under any other conditions.
3.3.2
STATUS REGISTER
The device contains a Status Register which may
be read to determine when a program or erase
operation is complete, and whether that operation
completed successfully. The Status Register may
be read at any time by writing the Read Status
command to the CUI. After writing this command,
all subsequent read operations output data from the
Status Register until another command is written to
the CUI. A Read Array command must be written to
the CUI to return to the read array mode.
The Status Register bits are output on DQ[0:7],
whether the device is in the byte-wide (x8) or word-
wide (x16) mode. In the word-wide mode the upper
byte, DQ[8:15], is set to 00H during a Read Status
command. In the byte-wide mode, DQ[8:14] are tri-
stated and DQ
15
/A
-1
retains the low order address
function.
Important: The contents of the Status Register
are latched on the falling edge of OE# or CE#,
whichever occurs last in the read cycle.
This
prevents possible bus errors which might occur if
the contents of the Status Register change while
reading the Status Register. CE# or OE# must be
toggled with each subsequent status read, or the
completion of a program or erase operation will not
be evident from the Status Register.
When the WSM is active, this register will indicate
the status of the WSM, and will also hold the bits
indicating whether or not the WSM was successful
in performing the desired operation.
3.3.2.1
Clearing the Status Register
The WSM sets status bits “3” through “7” to “1,” and
clears bits “6” and “7” to “0,” but cannot clear status
bits “3” through “5” to “0.” Bits 3 through 5 can only
be cleared by the controlling CPU through the use
of the Clear Status Register command. These bits
can indicate various error conditions. By allowing
the system software to control the resetting of these
bits, several operations may be performed (such as
cumulatively programming several bytes or erasing
multiple blocks in sequence). The Status Register
may then be read to determine if an error occurred
during that programming or erasure series. This
adds flexibility to the way the device may be
programmed or erased. To clear the Status
Register, the Clear Status Register command is
written to the CUI. Then, any other command may
be issued to the CUI. Note, again, that before a
read cycle can be initiated, a Read Array command
must be written to the CUI to specify whether the
read data is to come from the Memory Array, Status
Register, or Intelligent Identifier.
3.3.3
PROGRAM MODE
Programming is executed using a two-write
sequence. The Program Setup command is written
to the CUI followed by a second write which
相关PDF资料 |
PDF描述 |
|---|---|
| A28F400BX-B | 4-MBIT (256K x16. 512K x8) BOOT BLOCK FLASH MEMORY FAMILY |
| A28F400BR-TB | Toggle Switch; Circuitry:DPDT; Switch Operation:On-On; Contact Current Max:6A; Actuator Style:Bat; Switch Terminals:Through Hole; Current Rating:3A; Leaded Process Compatible:Yes; Mounting Type:PCB; Features:Standard Actuator RoHS Compliant: Yes |
| A28F400BX-T | 4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY |
| A29-1 | 10 TO 1500 MHz CASCADABLE AMPLIFIER |
| A290011SERIES | 128K X 8 Bit CMOS 5.0 Volt-only. Boot Sector Flash Memory |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A28F400BR-T/B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:A28F400BR-T/B |
| A28F400BR-TB | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT (256K X 16, 512K X 8) SmartVoltage BOOT BLOCK FLASH MEMORY FAMILY |
| A28F400BX-B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:4-MBIT (256K x16. 512K x8) BOOT BLOCK FLASH MEMORY FAMILY |
| A28F400BX-T | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:4-MBIT 256K x16, 512K x8 BOOT BLOCK FLASH MEMORY FAMILY |
| A28F400BX-T/B | 制造商:未知厂家 制造商全称:未知厂家 功能描述:A28F400BX-T/B |
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