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参数资料
| 型号： | A29400SERIES |
| 英文描述： | 512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only. Boot Sector Flash Memory |
| 中文描述： | 为512k × 8位/ 256 × 16位的CMOS 5.0伏特只。引导扇区闪存 |
| 文件页数： | 10/33页 |
| 文件大小： | 331K |
| 代理商： | A29400SERIES |
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A29400 Series
PRELIMINARY (December, 2002, Version 0.2)
10
AMIC Technology, Corp.
START
Write Program
Command
Sequence
Data Poll
from System
Verify Data
Last Address
Programming
Completed
No
Yes
Yes
Increment Address
Embedded
Program
algorithm in
progress
Note : See the appropriate Command Definitions table for
program command sequence.
Figure 2. Program Operation
Chip Erase Command Sequence
Chip erase is a six-bus-cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which in
turn invokes the Embedded Erase algorithm. The device does
not require the system to preprogram prior to erase. The
Embedded Erase algorithm automatically preprograms and
verifies the entire memory for an all zero data pattern prior to
electrical erase. The system is not required to provide any
controls or timings during these operations. The Command
Definitions table shows the address and data requirements
for the chip erase command sequence.
Any commands written to the chip during the Embedded
Erase algorithm are ignored. The system can determine the
status of the erase operation by using I/O
7
, I/O
6
, or I/O
2
. See
"Write Operation Status" for information on these status bits.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched.
Figure 3 illustrates the algorithm for the erase operation. See
the Erase/Program Operations tables in "AC Characteristics"
for parameters, and to the Chip/Sector Erase Operation
Timings for timing waveforms.
Sector Erase Command Sequence
Sector erase is a six-bus-cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the address of the sector to be
erased, and the sector erase command. The Command
Definitions table shows the address and data requirements
for the sector erase command sequence.
The device does not require the system to preprogram the
memory prior to erase. The Embedded Erase algorithm
automatically programs and verifies the sector for an all zero
data pattern prior to electrical erase. The system is not
required to provide any controls or timings during these
operations.
After the command sequence is written, a sector erase time-
out of 50
μ
s begins. During the time-out period, additional
sector addresses and sector erase commands may be
written. Loading the sector erase buffer may be done in any
sequence, and the number of sectors may be from one sector
to all sectors. The time between these additional cycles must
be less than 50
μ
s, otherwise the last address and command
might not be accepted, and erasure may begin. It is
recommended that processor interrupts be disabled during
this time to ensure all commands are accepted. The interrupts
can be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase
commands can be assumed to be less than 50
μ
s, the system
need not monitor I/O
3
. Any command other than Sector Erase
or Erase Suspend during the time-out period resets the
device to reading array data. The system must rewrite the
command sequence and any additional sector addresses and
commands.
The system can monitor I/O
3
to determine if the sector erase
timer has timed out. (See the " I/O
3
: Sector Erase Timer"
section.) The time-out begins from the rising edge of the final
WE
pulse in the command sequence.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignored.
When the Embedded Erase algorithm is complete, the device
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O
7
, I/O
6
, or I/O
2
. Refer to "Write
Operation Status" for information on these status bits.
相关PDF资料 |
PDF描述 |
|---|---|
| A29800SERIES | 1024K X 8 Bit / 512K X 16 Bit CMOS 5.0 Volt-only. Boot Sector Flash Memory |
| A2982ELW | Octal Peripheral Driver |
| A2982SLWTR | Octal Peripheral Driver |
| A2982 | 8-CHANNEL SOURCE DRIVERS |
| A2982SLW | 8-CHANNEL SOURCE DRIVERS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A29400TM-55 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| A29400TM-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| A29400TM-90 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| A29400TV-55 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory |
| A29400TV-70 | 制造商:AMICC 制造商全称:AMIC Technology 功能描述:512K X 8 Bit / 256K X 16 Bit CMOS 5.0 Volt-only, Boot Sector Flash Memory |
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