参数资料
型号: A3946KLBTR-T
厂商: Allegro Microsystems Inc
文件页数: 12/14页
文件大小: 0K
描述: IC CTLR MOSFET 16-SOIC
标准包装: 1
应用: DC 电机控制器,无刷(BLDC),3 相
输出数: 1
电源电压: 7 V ~ 60 V
工作温度: -40°C ~ 135°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 标准包装
其它名称: 620-1294-6
A3946
Half-Bridge Power MOSFET Controller
Pin-out Diagram
LP package
VREG
CP2
CP1
1
2
3
16
15
14
VBB
VREF
DT
PGND
GL
S
GH
BOOT
4
5
6
7
8
PAD
13
12
11
10
9
LGND
RESET
IN2
IN1
~FAULT
Terminal List Table
Name
VREG
CP2
CP1
PGND*
GL
S
GH
BOOT
~FAULT
IN1
IN2
RESET
LGND*
DT
VREF
VBB
PAD
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
Gate drive supply.
Charge pump capacitor, positive side. When not using the charge pump, leave this pin open.
Charge pump capacitor, negative side. When not using the charge pump, leave this pin open.
External ground. Internally connected to the power ground.
Low-side gate drive output for external MOSFET driver. External series gate resistor can be used to control
slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
Directly connected to the load terminal. The pin is also connected to the negative side of the bootstrap
capacitor and negative supply connection for the ? oating high-side drive.
High-side gate drive output for N-channel MOSFET driver. External series gate resistor can be used to
control slew rate seen at the power driver gate, thereby controlling the di/dt and dv/dt of the S pin output.
High-side connection for bootstrap capacitor, positive supply for the high-side gate drive.
Diagnostic output, open drain. Low during a fault condition.
Logic control.
Logic control.
Logic control input. When RESET = 0, the chip is in a very low power sleep mode.
External ground. Internally connected to the logic ground.
Dead Time. Connecting a resistor to GND sets the turn-on delay to prevent shoot-through. Forcing this
input high disables the dead time circuit and changes the logic truth table.
5 V internal reference decoupling terminal.
Supply Input.
Exposed thermal pad. Not connected to any pin, but should be externally connected to ground, to reduce
noise pickup by the pad.
The PGND pin (4) and LGND pin (13) grounds are NOT internally connected, and both must be connected to ground externally.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
12
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