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| 型号： | A3995SEVTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 4/9页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRIVER PWM DUAL 36-QFN |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器 |
| 输出数： | 2 |
| 电流 - 输出： | 2.4A |
| 电压 - 负载： | 8 V ~ 36 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN-EP（6x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1184-6 |
A3995
DMOS Dual Full Bridge PWM Motor Driver
ELECTRICAL CHARACTERISTICS 1 , valid at T A = 25 °C, V BB = 36 V, unless otherwise noted
Characteristics
Load Supply Voltage Range
Logic Supply Voltage Range
VDD Supply Current
Output On Resistance
V f , Outputs
Output Leakage
VBB Supply Current
Symbol
V BB
V DD
I DD
R DS(on)
I DSS
I BB
Test Conditions
Operating
Operating
Source driver, I OUT = –1.2 A, TJ = 25°C
Sink driver, I OUT = 1.2 A, TJ = 25°C
I OUT = 1.2 A
Outputs, V OUT = 0 to V BB
I OUT = 0 mA, outputs on, PWM = 50 kHz,
DC = 50%
Min.
8.0
3.0
–
–
–
–
–20
–
Typ. 2
–
–
7
350
350
–
–
–
Max.
36
5.5
10
450
450
1.3
20
8
Units
V
V
mA
m Ω
m Ω
V
μ A
mA
Control Logic
Logic Input Voltage
V IN(1)
V IN(0)
0.7×V DD
–
–
–
–
0.3×V DD
V
V
Logic Input Current
Input Hysteresis
Propagation Delay Times
Crossover Delay
Blank Time
VREF x Pin Input Voltage Range
VREF x Pin Reference Input Current
I IN
V hys
t pd
t COD
t BLANK
V REF x
I REF
V IN = 0 to 5 V
PWM change to source on
PWM change to source off
PWM change to sink on
PWM change to sink off
Operating
V REF = 1.5
–20
150
350
35
350
35
300
2.5
0.0
–
<1.0
300
550
–
550
–
425
3.2
–
–
20
500
1000
300
1000
250
1000
4
1.5
±1
μ A
mV
ns
ns
ns
ns
ns
μ s
V
μ A
Protection Circuits
VBB UVLO Threshold
VBB Hysteresis
VDD UVLO Threshold
VDD Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
V UV(VBB)
V UV(VBB)hys
V UV(VDD)
V UV(VDD)hys
T JTSD
T JTSDhys
V BB rising
V DD rising
7.3
400
2.65
75
155
–
7.6
500
2.8
105
165
15
7.9
600
2.95
125
175
–
V
mV
V
mV
°C
°C
1 For
input and output current specifications, negative current is defined as coming out of (sourcing) the specified device pin.
2 Typical
data are for initial design estimations only, and assume optimum manufacturing and application conditions. Performance may vary for indi-
vidual units, within the specified maximum and minimum limits.
3 V
ERR = [(V REF /3) – V SENSE ] / (V REF /3).
DC Control Logic
PHASE ENABLE MODE OUTA OUTB Function
1 1 1 H L Forward (slow decay SR)
1 1 0 H L Forward (fast decay SR)
0 1 1 L H Reverse (slow decay SR)
0 1 0 L H Reverse (fast decay SR)
X 0 1 L L Brake (slow decay SR)
1 0 0 L H Fast decay SR*
0 0 0 H L Fast decay SR*
* To prevent reversal of current during fast decay SR – the outputs will go to the high impedance state as the current gets near zero.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
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