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| 型号： | A3995SEVTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 6/9页 |
| 文件大小： | 0K |
| 描述： | IC MOTOR DRIVER PWM DUAL 36-QFN |
| 标准包装： | 1 |
| 应用： | PWM 电机驱动器 |
| 输出数： | 2 |
| 电流 - 输出： | 2.4A |
| 电压 - 负载： | 8 V ~ 36 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 36-VFQFN 裸露焊盘 |
| 供应商设备封装： | 36-QFN-EP（6x6） |
| 包装： | 标准包装 |
| 产品目录页面： | 1141 (CN2011-ZH PDF) |
| 其它名称： | 620-1184-6 |
A3995
DMOS Dual Full Bridge PWM Motor Driver
Functional Description
Device Operation The A3995 is designed to operate two
DC motors. The currents in each of the output full-bridges, all
N-channel DMOS, are regulated with fixed off-time pulse width
modulated (PWM) control circuitry. The peak current to each full
bridge is set by the value of an external current sense resistor,
R Sx , and a reference voltage, V REFx .
If the logic inputs are pulled up to VDD, it is good practice to use
a high value pullup resistor in order to limit current to the logic
inputs should an overvoltage event occur. Logic inputs include:
PHASEx, ENABLEx, and MODE.
Internal PWM Current Control Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, I TRIP . Initially, a diagonal pair
of source and sink DMOS outputs are enabled and current flows
through the motor winding and R Sx . When the voltage across the
current sense resistor equals the voltage on the VREFx pin, the
current sense comparator resets the PWM latch, which turns off
the source driver.
The maximum value of current limiting is set by the selection of
R S and the voltage at the VREF input with a transconductance
function approximated by:
I TripMax = V REF / (3×R S )
Note: It is critical to ensure that the maximum rating of ? 500 mV
on each SENSEx pin is not exceeded.
Fixed Off-Time The internal PWM current control circuitry
uses a one shot circuit to control the time the drivers remain off.
The one shot off-time, t off , is internally set to 30 μ s.
Blanking This function blanks the output of the current sense
comparator when the outputs are switched by the internal current
control circuitry. The comparator output is blanked to prevent
false detections of overcurrent conditions, due to reverse recovery
currents of the clamp diodes, or to switching transients related
to the capacitance of the load. The driver blank time, t BLANK , is
approximately 3 ? s.
Phase Input (PHASEx) The state of the PHASEx input
determines the direction of rotation of the motor.
Control Logic Dc motor commutation is accomplished by
applying a PWM signal together with the PHASE or ENABLE
inputs. Fast or slow current decay during the off-time is selected
via the MODE pin. Synchronous Rectification is always active
regardless of the state of the MODE pin.
Charge Pump (CP1 and CP2) The charge pump is used to
generate a gate supply greater than the V BB in order to drive the
source-side DMOS gates. A 0.1 ? F ceramic capacitor should be
connected between CP1 and CP2 for pumping purposes. A 0.1 ? F
ceramic capacitor is required between VCP and VBBx to act as a
reservoir to operate the high-side DMOS devices.
Shutdown In the event of a fault (excessive junction tem-
perature, or low voltage on VCP), the outputs of the device are
disabled until the fault condition is removed. At power-up, the
undervoltage lockout (UVLO) circuit disables the drivers.
Synchronous Rectification When a PWM-off cycle is
triggered by an internal fixed off-time cycle, load current will
recirculate. The A3995 synchronous rectification feature will
turn on the appropriate MOSFETs during the current decay. This
effectively shorts the body diode with the low R DS(on) driver. This
significantly lowers power dissipation. When a zero current level
is detected, synchronous rectification is turned off to prevent
reversal of the load current.
MODE Control input MODE is used to toggle between fast
decay mode and slow decay mode. A logic high puts the device
in slow decay mode. Synchronous rectification is always enabled
when ENABLE is low.
Braking The Braking function is implemented by driving the
device in slow decay mode via the MODE pin and applying an
ENABLE chop command. Because it is possible to drive current
in both directions through the DMOS switches, this configura-
tion effectively shorts the motor-generated BEMF as long as the
ENABLE chop mode is asserted. The maximum current can be
approximated by V BEMF /R L . Care should be taken to ensure that
the maximum ratings of the device are not exceeded in worst case
braking situations: high speed and high inertia loads.
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
6
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