
ProASIC3E Flash Family FPGAs
Revision 13
2-37
3.3 V PCI, 3.3 V PCI-X
Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI Bus
applications.
AC loadings are defined per the PCI/PCI-X specifications for the datapath; Microsemi loadings for enable
AC loadings are defined per PCI/PCI-X specifications for the datapath; Microsemi loading for tristate is
Timing Characteristics
Table 2-45 Minimum and Maximum DC Input and Output Levels
3.3 V PCI/PCI-X
VIL
VIH
VOL
VOH IOL IOH
IOSL
IOSH
IIL1 IIH2
Drive Strength
Min.
V
Max.
V
Min.
V
Max.
V
Max.
V
Min.
VmA mA
Max.
mA3
Max.
mA3
A4 A4
Per PCI specification
Per PCI curves
10 10
Notes:
1. IIL is the input leakage current per I/O pin over recommended operation conditions where –0.3 V< VIN < VIL.
2. IIH is the input leakage current per I/O pin over recommended operating conditions VIH < VIN< VCCI. Input current is
larger when operating outside recommended ranges.
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Figure 2-11 AC Loading
Test Point
Enable Path
R to VCCI for tLZ / tZL / tZLS
10 pF for tZH / tZHS / tZL / tZLS
10 pF for tHZ / tLZ
R to GND for tHZ / tZH / tZHS
R = 1 k
Test Point
Datapath
R = 25
R to VCCI for tDP (F)
R to GND for tDP (R)
Table 2-46 AC Waveforms, Measuring Points, and Capacitive Loads
Input Low (V)
Input High (V)
Measuring Point* (V)
VREF (typ.) (V)
CLOAD (pF)
0
3.3
0.285 * VCCI for tDP(R)
0.615 * VCCI for tDP(F)
–10
Table 2-47 3.3 V PCI/PCI-X
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
Std.
0.66
2.81
0.04
1.05
1.67
0.43
2.86
2.00
3.28
3.61
5.09
4.23
ns
–1
0.56
2.39
0.04
0.89
1.42
0.36
2.43
1.70
2.79
3.07
4.33
3.60
ns
–2
0.49
2.09
0.03
0.78
1.25
0.32
2.13
1.49
2.45
2.70
3.80
3.16
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.