参数资料
型号: A3PE1500-PQG208
元件分类: FPGA
英文描述: FPGA, 38400 CLBS, 1500000 GATES, PQFP208
封装: 28 X 28 MM, 3.40 MM HEIGHT, 0.50 MM PITCH, GREEN, PLASTIC, QFP-208
文件页数: 105/152页
文件大小: 4932K
代理商: A3PE1500-PQG208
ProASIC3E DC and Switching Characteristics
2- 44
v1.2
SSTL3 Class I
Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support
Class I. This provides a differential amplifier input buffer and a push-pull output buffer.
Timing Characteristics
Table 2-68 Minimum and Maximum DC Input and Output Levels
SSTL3 Class I
VIL
VIH
VOL
VOH
IOL IOH
IOSL
IOSH
IIL IIH
Drive
Strength
Min., V Max., V
Min., V
Max., V Max., V Min., V mA mA Max., mA1 Max., mA1 A2 A2
14 mA
–0.3
VREF – 0.2 VREF + 0.2
3.6
0.7
VCCI – 1.1 14 14
54
51
10
Notes:
1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
2. Currents are measured at 85°C junction temperature.
Figure 2-19 AC Loading
Table 2-69 AC Waveforms, Measuring Points, and Capacitive Loads
Input LOW (V)
Input HIGH (V)
Measuring
Point* (V)
VREF (typ.) (V)
VTT (typ.) (V)
CLOAD (pF)
VREF – 0.2
VREF + 0.2
1.5
1.485
30
* Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.
Test Point
30 pF
50
25
SSTL3
Class I
VTT
Table 2-70 SSTL3 Class I
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,
Worst-Case VCCI =3.0 V, VREF = 1.5 V
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
–F
0.79
2.77
0.05
1.50
0.51
2.82
2.21
5.51
4.89
ns
Std.
0.66
2.31
0.04
1.25
0.43
2.35
1.84
4.59
4.07
ns
–1
0.56
1.96
0.04
1.06
0.36
2.00
1.56
3.90
3.46
ns
–2
0.49
1.72
0.03
0.93
0.32
1.75
1.37
3.42
3.04
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating
values.
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