参数资料
型号: A3PN125-FVQG100
元件分类: FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, PQFP100
封装: 14 X 14 MM, 1.20 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, VQFP-100
文件页数: 13/92页
文件大小: 3184K
代理商: A3PN125-FVQG100
ProASIC3 nano DC and Switching Characteristics
2- 6
A d vance v0.2
Calculating Power Dissipation
Quiescent Supply Current
Power per I/O Pin
Table 2-7
Quiescent Supply Current Characteristics
A3PN010
A3PN015
A3PN020
A3PN060
A3PN125
A3PN250
Typical (25°C)
1 mA
2 mA
3 mA
Max. (Commercial)
5 mA
10 mA
20 mA
Max. (Industrial)
8 mA
15 mA
30 mA
Notes:
1. IDD Includes VCC, VPUMP, and VCCI, currents. Values do not include I/O static contribution, which
is shown in Table 2-9.
2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD
and higher I/O leakage.
Table 2-8
Summary of I/O Input Buffer Power (Per Pin) – Default I/O Software Settings
VCCI (V)
Dynamic Power
PAC9 (W/MHz)
*
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
3.3
16.26
3.3 V LVTTL / 3.3 V LVCMOS – Schmitt Trigger
3.3
18.95
2.5 V LVCMOS
2.5
4.59
2.5 V LVCMOS – Schmitt Trigger
2.5
6.01
1.8 V LVCMOS
1.8
1.61
1.8 V LVCMOS – Schmitt Trigger
1.8
1.70
1.5 V LVCMOS (JESD8-11)
1.5
0.96
1.5 V LVCMOS (JESD8-11) – Schmitt Trigger
1.5
0.90
Note: *PAC9 is the total dynamic power measured on VCCI.
Table 2-9
Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1
CLOAD (pF)
2
VCCI (V)
Dynamic Power
PAC10 (W/MHz)
3
Single-Ended
3.3 V LVTTL / 3.3 V LVCMOS
10
3.3
162.43
2.5 V LVCMOS
10
2.5
92.49
1.8 V LVCMOS
10
1.8
47.48
1.5 V LVCMOS (JESD8-11)
10
1.5
32.75
Notes:
1. Dynamic power consumption is given for standard load and software default drive strength
and output slew.
2. Values are for A3PN020, A3PN015, and A3PN010. A3PN060, A3PN125, and A3PN250 have a
default loading of 35 pF.
3. PAC10 is the total dynamic power measured on VCCI.
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