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参数资料
型号： A40MX04-FPL44
元件分类： FPGA
英文描述： FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC44
封装： PLASTIC, LCC-44
文件页数： 101/124页
文件大小： 3142K
代理商： A40MX04-FPL44
40MX and 42MX FPGA Families
1- 72
v6.1
TTL Output Module Timing5 (Continued)
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
2.9
3.3
3.7
4.4
6.1
ns
tGHL
G-to-Pad LOW
2.9
3.3
3.7
4.4
6.1
ns
tLSU
I/O Latch Output Set-Up
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Output Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
CMOS Output Module Timing5
tDLH
Data-to-Pad HIGH
3.5
3.9
4.5
5.2
7.3
ns
tDHL
Data-to-Pad LOW
2.5
2.7
3.1
3.6
5.1
ns
tENZH
Enable Pad Z to HIGH
2.7
3.0
3.3
3.9
5.5
ns
tENZL
Enable Pad Z to LOW
2.9
3.3
3.7
4.3
6.1
ns
tENHZ
Enable Pad HIGH to Z
5.3
5.8
6.6
7.8
10.9
ns
tENLZ
Enable Pad LOW to Z
4.9
5.5
6.2
7.3
10.2
ns
tGLH
G-to-Pad HIGH
5.0
5.6
6.3
7.5
10.4
ns
tGHL
G-to-Pad LOW
5.0
5.6
6.3
7.5
10.4
ns
tLSU
I/O Latch Set-Up
0.5
0.6
0.7
1.0
ns
tLH
I/O Latch Hold
0.0
ns
tLCO
I/O Latch Clock-to-Out (Pad-to-
Pad) 32 I/O
5.7
6.3
7.1
8.4
11.8
ns
tACO
Array Latch Clock-to-Out (Pad-
to-Pad) 32 I/O
7.8
8.6
9.8
11.5
16.1
ns
dTLH
Capacitive Loading, LOW to HIGH
0.07
0.08
0.09
0.10
0.14
ns/pF
dTHL
Capacitive Loading, HIGH to LOW
0.07
0.08
0.09
0.10
0.14
ns/pF
Table 38
A42MX36 Timing Characteristics (Nominal 5.0V Operation)
(Worst-Case Commercial Conditions, VCCA = 4.75V, TJ = 70°C)
‘–3’ Speed
‘–2’ Speed
‘–1’ Speed
‘Std’ Speed
‘–F’ Speed
Parameter Description
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max. Units
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual performance.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
5. Delays based on 35 pF loading.
相关PDF资料
PDF描述
A40MX04-FPL68X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
A40MX04-FPL68 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC68
A40MX04-FPL84X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPL84 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQCC84
A40MX04-FPQ100X79 FPGA, 547 CLBS, 6000 GATES, 48 MHz, PQFP100
相关代理商/技术参数
参数描述
A40MX04-FPL44I 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPL44M 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPL68 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:152 系列:IGLOO PLUS LAB/CLB数:- 逻辑元件/单元数:792 RAM 位总计:- 输入/输出数:120 门数:30000 电源电压:1.14 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 85°C 封装/外壳:289-TFBGA，CSBGA 供应商设备封装:289-CSP（14x14）
A40MX04-FPL68I 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
A40MX04-FPL68M 制造商:未知厂家 制造商全称:未知厂家 功能描述:Field Programmable Gate Array (FPGA)
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