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| 型号： | A40MX04-PL84MX79 |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC84 |
| 封装： | PLASTIC, LCC-84 |
| 文件页数： | 32/124页 |
| 文件大小： | 3142K |
| 代理商： | A40MX04-PL84MX79 |
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40MX and 42MX FPGA Families
v6.1
1-9
Fixed Capacitance Values for MX FPGAs (pF)
Test Circuitry and Silicon Explorer II Probe
MX devices contain probing circuitry that provides built-
in access to every node in a design, via the use of Silicon
Explorer II. Silicon Explorer II is an integrated hardware
and software solution that, in conjunction with the
Designer software, allow users to examine any of the
internal nets of the device while it is operating in a
prototyping or a production system. The user can probe
into an MX device without changing the placement and
routing of the design and without using any additional
resources. Silicon Explorer II's noninvasive method does
not alter timing or loading effects, thus shortening the
debug cycle and providing a true representation of the
device under actual functional situations.
Silicon
Explorer
II
samples
data
at
100
MHz
(asynchronous) or 66 MHz (synchronous). Silicon Explorer
II attaches to a PC's standard COM port, turning the PC
into a fully functional 18-channel logic analyzer. Silicon
Explorer II allows designers to complete the design
verification
process
at
their
desks
and
reduces
verification time from several hours per cycle to a few
seconds.
Silicon Explorer II is used to control the MODE, DCLK, SDI
and SDO pins in MX devices to select the desired nets for
debugging. The user simply assigns the selected internal
nets in the Silicon Explorer II software to the PRA/PRB
output pins for observation. Probing functionality is
activated when the MODE pin is held HIGH.
Figure 1-12 illustrates the interconnection between
Silicon Explorer II and 40MX devices, while Figure 1-13
on page 1-10 illustrates the interconnection between
Silicon Explorer II and 42MX devices
To allow for probing capabilities, the security fuses must
not be programmed. (Refer to <zBlue>“User Security”
section on page 6 for the security fuses of 40MX and
42MX devices). Table 2 on page 1-10 summarizes the
possible device configurations for probing.
PRA and PRB pins are dual-purpose pins. When the
"Reserve
Probe
Pin"
is
checked
in
the
Designer software, PRA and PRB pins are reserved as
dedicated outputs for probing. If PRA and PRB pins are
required as user I/Os to achieve successful layout and
"Reserve Probe Pin" is checked, the layout tool will
override the option and place user I/Os on PRA and PRB
pins.
CEQM = Equivalent capacitance of logic modules in pF
CEQI = Equivalent capacitance of input buffers in pF
CEQO = Equivalent capacitance of output buffers in pF
CEQCR = Equivalent capacitance of routed array clock in
pF
CL
= Output load capacitance in pF
fm
= Average logic module switching rate in MHz
fn
= Average input buffer switching rate in MHz
fp
= Average output buffer switching rate in MHz
fq1
= Average first routed array clock rate in MHz
fq2
= Average second routed array clock rate in MHz
Device Type
r1
routed_Clk1
r2
routed_Clk2
A40MX02
41.4
N/A
A40MX04
68.6
N/A
A42MX09
118
A42MX16
165
A42MX24
185
A42MX36
220
Figure 1-12 Silicon Explorer II Setup with 40MX
40MX
Silicon
Explorer II
PRA
PRB
SDO
DCLK
SDI
MODE
Serial Connection
to Windows PC
16 Logic Analyzer Channels
相关PDF资料 |
PDF描述 |
|---|---|
| A40MX04-PL84M | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC84 |
| A40MX04-PL84X79 | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC84 |
| A40MX04-PL84 | FPGA, 547 CLBS, 6000 GATES, 80 MHz, PQCC84 |
| A40MX04-PQ100AX79 | FPGA, 547 CLBS, 6000 GATES, 116 MHz, PQFP100 |
| A40MX04-PQ100A | FPGA, 547 CLBS, 6000 GATES, 116 MHz, PQFP100 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A40MX04-PLG44 | 功能描述:IC FPGA 69I/O 44PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:24 系列:ECP2 LAB/CLB数:1500 逻辑元件/单元数:12000 RAM 位总计:226304 输入/输出数:131 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） |
| A40MX04-PLG44I | 功能描述:IC FPGA MX SGL CHIP 6K 44-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17） |
| A40MX04-PLG44M | 制造商:Microsemi Corporation 功能描述:FPGA 6K GATES 547 CELLS 83MHZ/139MHZ 0.45UM 3.3V/5V 44PLCC - Rail/Tube 制造商:Microsemi Corporation 功能描述:IC FPGA 34 I/O 44PLCC |
| A40MX04-PLG68 | 功能描述:IC FPGA 69I/O 68PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:24 系列:ECP2 LAB/CLB数:1500 逻辑元件/单元数:12000 RAM 位总计:226304 输入/输出数:131 门数:- 电源电压:1.14 V ~ 1.26 V 安装类型:表面贴装 工作温度:0°C ~ 85°C 封装/外壳:208-BFQFP 供应商设备封装:208-PQFP（28x28） |
| A40MX04-PLG68I | 功能描述:IC FPGA MX SGL CHIP 6K 68-PLCC RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:90 系列:ProASIC3 LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:36864 输入/输出数:157 门数:250000 电源电压:1.425 V ~ 1.575 V 安装类型:表面贴装 工作温度:-40°C ~ 125°C 封装/外壳:256-LBGA 供应商设备封装:256-FPBGA（17x17） |
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