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参数资料
| 型号： | A42MX36-BGG272A |
| 元件分类： | FPGA |
| 英文描述： | FPGA, 54000 GATES, PBGA272 |
| 封装： | PLASTIC, BGA-272 |
| 文件页数： | 43/76页 |
| 文件大小： | 429K |
| 代理商： | A42MX36-BGG272A |
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MX Automotive Family FPGAs
1- 4 2
v2 .0
Pin Descriptions
CLK, CLKA,B, I/O
Global Clock (Input)
TTL clock inputs for clock distribution networks. The
clock input is buffered prior to clocking the logic
modules. This pin can also be used as an I/O.
DCLK, I/O
Diagnostic Clock (Input)
TTL clock input for diagnostic probe and device
programming. DCLK is active when the MODE pin is
HIGH. This pin functions as an I/O when the MODE pin is
LOW.
GND
Ground (Input)
Input LOW supply voltage.
I/O
Input/Output (Input, Output)
Input, output, tri-state, or bi-directional buffer. Input
and output levels are compatible with standard TTL and
CMOS specifications. Unused I/O pins are automatically
driven LOW by the Designer Series software.
MODE
Mode (Input)
Controls the use of multifunction pins (DCLK, PRA, PRB,
SDI, TDO). To provide verification capability, the MODE
pin should be held HIGH. To facilitate this, the MODE pin
should be tied to GND through a 10K
resistor so that
the MODE pin can be pulled HIGH when required.
NC
No Connection
This pin is not connected to circuitry within the device.
These pins can be driven to any voltage or can be left
floating with no effect on the operation of the device.
PRA, PRB, I/O
Probe
The pins are used for real-time diagnostic output of any
signal path within the device. Each pin can be used as a
user-defined I/O when verification has been completed.
The pin’s probe capabilities can be permanently disabled
to protect programmed design confidentiality. PRA and
PRB are accessible when the MODE pin is HIGH. These
pins function as I/Os when the MODE pin is LOW.
QCLKA,B,C,D, I/O
Quadrant Clock (Input/Output)
Quadrant clock inputs. When not used as a register
control signal, these pins can function as general-
purpose I/Os.
SDI, I/O
Serial Data Input
Serial data input for diagnostic probe and device
programming. SDI is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO, TDO, I/O
Serial Data Output
Serial data output for diagnostic probe and device
programming. SDO is active when the MODE pin is HIGH.
This pin functions as an I/O when the MODE pin is LOW.
SDO is not available for 40MX devices.
TCK, I/O
Test Clock
Clock signal to shift the Boundary Scan Test (BST) data
into the device. This pin functions as an I/O when the test
fuse is not programmed. BST pins are only available in
the A42MX24 and A42MX36 devices.
TDI, I/O
Test Data In
Serial data input for BST instructions and data. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when the test fuse is not programmed. BST pins
are only available in the A42MX24 and A42MX36
devices.
TDO, I/O
Test Data Out
Serial data output for BST instructions and test data. This
pin functions as an I/O when the test fuse is not
programmed. BST pins are only available in the
A42MX24 and A42MX36 devices.
TMS, I/O
Test Mode Select
Serial data input for boundary scan test mode. Data is
shifted in on the rising edge of TCK. This pin functions as
an I/O when the test fuse is not programmed. BST pins
are only available in the A42MX24 and A42MX36
devices.
VCC
Supply Voltage Input
Input HIGH supply voltage for 40 MX devices.
VCCA
Supply Voltage Input
Input HIGH supply voltage, supplies array core for 42MX
devices.
VCCI
Supply Voltage Input
Input HIGH supply voltage, supplies I/O cells only for
42MX devices.
WD, I/O
Wide Decode Output
When a wide decode module is used in a 42MX device,
this pin can be used as a dedicated output from the wide
decode
module.
This
direct
connection
eliminates
additional interconnect delays associated with regular
logic modules. To implement the direct I/O connection,
connect an output buffer of any type to the output of
the wide decode macro and place this output on one of
the reserved WD pins. When a wide decode module is
not used, this pin functions as a regular I/O pin.
相关PDF资料 |
PDF描述 |
|---|---|
| A42MX36-CQ208A | FPGA, 54000 GATES, CQFP208 |
| A42MX36-CQ256A | FPGA, 54000 GATES, CQFP256 |
| A42MX36-1RQ208I | FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208 |
| A42MX36-1RQ208 | FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208 |
| A42MX36-1RQG208I | FPGA, 2438 CLBS, 36000 GATES, 91 MHz, PQFP208 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| A42MX36-BGG272I | 功能描述:IC FPGA MX SGL CHIP 54K 272-PBGA RoHS:是 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A42MX36-BGG272M | 制造商:Microsemi Corporation 功能描述:FPGA 42MX Family 54K Gates 1184 Cells 79MHz/131MHz 0.45um Technology 3.3V/5V 272-Pin BGA 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 272BGA - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 202 I/O 272PBGA |
| A42MX36-CQ208 | 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A42MX36-CQ208B | 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP RoHS:否 类别:集成电路 (IC) >> 嵌入式 - FPGA（现场可编程门阵列） 系列:MX 标准包装:1 系列:ProASICPLUS LAB/CLB数:- 逻辑元件/单元数:- RAM 位总计:129024 输入/输出数:248 门数:600000 电源电压:2.3 V ~ 2.7 V 安装类型:表面贴装 工作温度:- 封装/外壳:352-BFCQFP，带拉杆 供应商设备封装:352-CQFP（75x75） |
| A42MX36-CQ208M | 制造商:Microsemi Corporation 功能描述:FPGA 54K GATES 1184 CELLS 79MHZ/131MHZ 0.45UM 3.3V/5V 208CQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 176 I/O 208CQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 54K 208-CQFP |
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