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参数资料
| 型号： | A4988SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 10/20页 |
| 文件大小： | 0K |
| 描述： | IC MICROSTEPPER MOTOR DRVR 28QFN |
| 特色产品： | A498x Motor Driver Family |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±2A |
| 电压 - 负载： | 8 V ~ 35 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN/MLP 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 其它名称： | 620-1343-6 |
A4988
DMOS Microstepping Driver with Translator
And Overcurrent Protection
V REG (VREG) . This internally-generated voltage is used to
operate the sink-side FET outputs. The nominal output voltage
of the VREG terminal is 7 V. The VREG pin must be decoupled
with a 0.22 μ F ceramic capacitor to ground. V REG is internally
monitored. In the case of a fault condition, the FET outputs of the
A4988 are disabled.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Enable Input ( ˉEˉ ˉNˉ ˉAˉ ˉBˉ ˉLˉ ˉEˉ ) . This input turns on or off all of the
5 A / div.
Fault
latched
FET outputs. When set to a logic high, the outputs are disabled.
When set to a logic low, the internal control enables the outputs
as required. The translator inputs STEP, DIR, and MSx, as well as
the internal sequencing logic, all remain active, independent of the
ˉEˉ ˉNˉ ˉAˉ ˉBˉ ˉLˉ ˉEˉ input state.
Shutdown. In the event of a fault, overtemperature (excess T J )
or an undervoltage (on VCP), the FET outputs of the A4988 are
disabled until the fault condition is removed. At power-on, the
UVLO (undervoltage lockout) circuit disables the FET outputs
and resets the translator to the Home state.
Sleep Mode ( ˉSˉ ˉLˉ ˉEˉ ˉEˉ ˉPˉ ). To minimize power consumption
when the motor is not in use, this input disables much of the
internal circuitry including the output FETs, current regulator,
and charge pump. A logic low on the Sˉ ˉLˉ ˉEˉ ˉEˉ ˉP pin puts the A4988
into Sleep mode. A logic high allows normal operation, as well as
start-up (at which time the A4988 drives the motor to the Home
microstep position). When emerging from Sleep mode, in order
to allow the charge pump to stabilize, provide a delay of 1 ms
before issuing a Step command.
Mixed Decay Operation. The bridge operates in Mixed
Decay mode, depending on the step sequence, as shown in fig-
t →
Figure 4. Short-to-ground event
5 A / div.
Fixed off-time
t →
Figure 5. Shorted load (OUTxA → OUTxB) in
Slow decay mode
ures 8 through 12. As the trip point is reached, the A4988 initially
goes into a fast decay mode for 31.25% of the off-time, t OFF .
After that, it switches to Slow Decay mode for the remainder of
t OFF . A timing diagram for this feature appears in figure 7.
Synchronous Rectification . When a PWM-off cycle is
triggered by an internal fixed-off time cycle, load current recircu-
lates according to the decay mode selected by the control logic.
5 A / div.
Fixed off-time
This synchronous rectification feature turns on the appropriate
FETs during current decay, and effectively shorts out the body
diodes with the low FET R DS(ON) . This reduces power dissipation
significantly, and can eliminate the need for external Schottky
diodes in many applications. Synchronous rectification turns off
when the load current approaches zero (0 A), preventing reversal
of the load current.
Fast decay portion
(direction change)
t →
Figure 6. Shorted load (OUTxA → OUTxB) in
Mixed decay mode
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
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