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| 型号： | A4988SETTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/20页 |
| 文件大小： | 0K |
| 描述： | IC MICROSTEPPER MOTOR DRVR 28QFN |
| 特色产品： | A498x Motor Driver Family |
| 标准包装： | 1 |
| 应用： | 步进电机驱动器 |
| 输出数： | 1 |
| 电流 - 输出： | ±2A |
| 电压 - 负载： | 8 V ~ 35 V |
| 电源电压： | 3 V ~ 5.5 V |
| 工作温度： | -20°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-VFQFN 裸露焊盘 |
| 供应商设备封装： | 28-QFN/MLP 裸露焊盘（5x5） |
| 包装： | 标准包装 |
| 其它名称： | 620-1343-6 |
A4988
DMOS Microstepping Driver with Translator
And Overcurrent Protection
tion of current flow in each winding. The size of the increment is
determined by the combined state of the MSx inputs.
Direction Input (DIR). This determines the direction of rota-
tion of the motor. Changes to this input do not take effect until the
next STEP rising edge.
Internal PWM Current Control. Each full-bridge is con-
trolled by a fixed off-time PWM current control circuit that limits
the load current to a desired value, I TRIP . Initially, a diagonal pair
of source and sink FET outputs are enabled and current flows
through the motor winding and the current sense resistor, R S x .
When the voltage across R S x equals the DAC output voltage, the
current sense comparator resets the PWM latch. The latch then
turns off the appropriate source driver and initiates a fixed off
time decay mode
The maximum value of current limiting is set by the selection of
R S x and the voltage at the VREF pin. The transconductance func-
tion is approximated by the maximum value of current limiting,
I TripMAX (A), which is set by
I TripMAX = V REF / ( 8 ? R S )
where R S is the resistance of the sense resistor ( Ω ) and V REF is
the input voltage on the REF pin (V).
The DAC output reduces the V REF output to the current sense
comparator in precise steps, such that
I trip = (%I TripMAX / 100) × I TripMAX
(See table 2 for %I TripMAX at each step.)
It is critical that the maximum rating (0.5 V) on the SENSE1 and
SENSE2 pins is not exceeded.
Fixed Off-Time. The internal PWM current control circuitry
uses a one-shot circuit to control the duration of time that the
DMOS FETs remain off. The off-time, t OFF , is determined by the
ROSC terminal. The ROSC terminal has three settings:
? ROSC tied to VDD — off-time internally set to 30 μ s, decay
? ROSC through a resistor to ground — off-time is determined
by the following formula, the decay mode is automatic Mixed
decay for all step modes.
t OFF ≈ R OSC ? 825
Where t OFF is in μ s.
Blanking. This function blanks the output of the current sense
comparators when the outputs are switched by the internal current
control circuitry. The comparator outputs are blanked to prevent
false overcurrent detection due to reverse recovery currents of the
clamp diodes, and switching transients related to the capacitance
of the load. The blank time, t BLANK ( μ s), is approximately
t BLANK ≈ 1 μ s
Shorted-Load and Short-to-Ground Protection.
If the motor leads are shorted together, or if one of the leads is
shorted to ground, the driver will protect itself by sensing the
overcurrent event and disabling the driver that is shorted, protect-
ing the device from damage. In the case of a short-to-ground, the
device will remain disabled (latched) until the Sˉ ˉLˉ ˉEˉ ˉEˉ ˉP input goes
high or VDD power is removed. A short-to-ground overcurrent
event is shown in figure 4.
When the two outputs are shorted together, the current path is
through the sense resistor. After the blanking time ( ≈ 1 μ s) expires,
the sense resistor voltage is exceeding its trip value, due to the
overcurrent condition that exists. This causes the driver to go into
a fixed off-time cycle. After the fixed off-time expires the driver
turns on again and the process repeats. In this condition the driver
is completely protected against overcurrent events, but the short
is repetitive with a period equal to the fixed off-time of the driver.
This condition is shown in figure 5.
During a shorted load event it is normal to observe both a posi-
tive and negative current spike as shown in figure 3, due to the
direction change implemented by the Mixed decay feature. This
is shown in figure 6. In both instances the overcurrent circuitry is
protecting the driver and prevents damage to the device.
Charge Pump (CP1 and CP2). The charge pump is used to
generate a gate supply greater than that of VBB for driving the
source-side FET gates. A 0.1 μ F ceramic capacitor, should be
connected between CP1 and CP2. In addition, a 0.1 μ F ceramic
decay mode is set to Slow decay
mode is automatic Mixed decay except when in full step where capacitor is required between VCP and VBB, to act as a reservoir
for operating the high-side FET gates.
? ROSC tied directly to ground — off-time internally set to
30 μ s, current decay is set to Mixed decay for both increasing
and decreasing currents for all step modes.
Capacitor values should be Class 2 dielectric ±15% maximum,
or tolerance R, according to EIA (Electronic Industries Alliance)
specifications.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
9
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