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参数资料
| 型号： | a6402 |
| 厂商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用异步接收/传送器) |
| 中文描述： | 通用异步接收器/发送器（通用异步接收/传送器） |
| 文件页数： | 5/8页 |
| 文件大小： | 241K |
| 代理商： | A6402 |
Altera Corporation
61
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
Master Reset
When the
asynchronously cleared and
assertion of
mr
condition does not affect the receiver buffer register. The
must be pulsed high at least once after power-up. When
deasserted, normal operation resumes at the next rising edge of
or
rrc
.
mr
input is asserted, the
pe
and
,
fe
tre
,
oe
are asserted. The
, and
dr
outputs are
tbre
also sets all state machines to a default idle state. This
mr
mr
input
is
trc
1
Once the
condition available is through asserting
pe
,
fe
, and
oe
outputs are set, the only exit
mr
.
Control Register
The control register contains the configuration of the data word,
including the number of bits, calculated parity, and the number of
stop bits. The
crl
input, an active high register enable, controls how
the data word is loaded into the control register. When
asserted, the
cls2
,
cls1
,
pi
,
epe
, and
sbs
inputs are loaded on the
next rising edge of the
trc
input.
crl
is
Transmitter
The transmitter consists of the following elements:
I
Transmitter control
—The transmitter control contains three
interconnected state machines. The first state machine regulates
the baud rate by performing a divide-by-16 operation on the
trc
input. The second state machine detects the low-to-high
transition on
ntbrl
, starts the serial transmission through
tro
,
transfers data from the transmitter buffer register to the
transmitter register, and generates the status signals
tbre
and
tre
. The third state machine controls the multiplexing of data
bits to the
tro
output.
I
Transmitter buffer register
—The transmitter buffer register is
loaded via
ntbrl
, an active-low register enable, that causes
tbr[7..0]
to be loaded from the microprocessor on the next
trc
clock edge.
I
Transmitter register
—The transmitter register loads the data
from the transmitter buffer register and holds that data until
transmission is complete.
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