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参数资料
| 型号： | a6402 |
| 厂商： | Altera Corporation |
| 英文描述： | Universal Asynchronous Receiver/Transmitter(通用异步接收/传送器) |
| 中文描述： | 通用异步接收器/发送器（通用异步接收/传送器） |
| 文件页数： | 6/8页 |
| 文件大小： | 241K |
| 代理商： | A6402 |
62
Altera Corporation
a6402 Universal Asynchronous Receiver/Transmitter Data Sheet
I
Parity generator
—The parity generator calculates the
appropriate parity value depending on the
epe
input (even or
odd parity) and the
cls
inputs (data word length).
I
Transmitter multiplexer
—The transmitter multiplexer selects a
single-bit data value and drives the
tro
output. Inputs to the
transmitter multiplexer include the start bit, all eight bits from
the transmitter register, the parity bit, and a stop or idle bit.
Receiver
The receiver consists of the following elements:
I
Receiver control
—The receiver control contains three
interconnected state machines. The first state machine performs
a divide-by-16 operation on the
rrc
clock to determine when to
sample the
rri
serial input. The second state machine detects
the high-to-low transition on
rri
, determines if a valid start bit
has been received, transfers data from the receiver register to the
receiver buffer register, and generates the status signals
dr
and
oe
. The third state machine loads the individual bits of the
receiver register and the
fe
and
pe
outputs.
I
Receiver register
—The receiver register loads the number of data
bits determined by the
cls
inputs. If the data word is less than
eight bits, the data is right-justified with the MSBs filled with
logic lows. When the stop bit is detected, the receiver register
transfers its contents to the receiver buffer register.
I
Parity check
—The parity check calculates the parity of the data
word and the parity bit. If an error occurs, the
pe
output is
asserted. Once asserted, the
pe
output can only be cleared by
asserting the
mr
input.
I
Stop check
—The stop check samples the middle of the first
expected stop bit. If an error occurs, the
fe
output is asserted.
Once asserted, the
fe
output can only be cleared by asserting
the
mr
input.
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