参数资料
型号: A8509GLPTR-T
厂商: Allegro Microsystems Inc
文件页数: 10/28页
文件大小: 0K
描述: IC LED DVR WHITE 4X120MA 24TSSOP
标准包装: 8,000
拓扑: PWM,SEPIC,升压(升压)
输出数: 4
内部驱动器:
类型 - 主要: 背光
类型 - 次要: 白色 LED
频率: 300kHz ~ 800kHz
电源电压: 9 V ~ 40 V
安装类型: 表面贴装
封装/外壳: 24-TSSOP(0.173",4.40mm)裸露焊盘
供应商设备封装: 24-TSSOP 裸露焊盘
包装: 带卷 (TR)
工作温度: -40°C ~ 105°C
A8509
Frequency selection
Wide Input Voltage Range, High Efficiency
4-Channel Fault Tolerant LED Driver
V OUT
The switching frequency on the boost regulator is set by con-
necting a resistor between the FSET/SYNC pin and ground.
C2
V FSET/SYNC
The switching frequency range is 300 to 800 kHz, with example
values of:
I IN
FSET/SYNC shorted to GND
R FSET Value
(k Ω )
7.5
10
Swtiching Frequency, f SW
(kHz)
800
600
C1
C3
I OUT
The relationship of R FSET and f SW is shown in figure 9.
The FSET/SYNC pin has short-to-ground protection. If the
FSET/SYNC pin is held low for more than 4 μ s typical, the
A8509 will stop switching and disable the LEDx pins (see figures
10 and 11). If the FSET/SYNC pin is released at any time after
7 μ s, the A8509 will proceed to soft start but will not perform the
LED detection phase.
C4
t
Figure 10. Shutdown when the FSET/SYNC pin is shorted to ground;
shows V OUT (ch1, 10 V/div.), V FSET/SYNC (ch2, 1 V/div.), I IN (ch3, 2 A/div.),
and I OUT (ch4, 500 mA/div.), t = 200 μ s/div.
V OUT
V FSET/SYNC
FSET/SYNC shorted to GND
Synchronization
C2
I IN
The A8509 can also be synchronized by using an external clock
connected to the FSET/SYNC pin. The synchronization func-
tion of IC was designed to work with a push-pull type of clock
driver. The amplitude of the clock signal should be between
1.5 and 3.3 V. The synchronization clock should have duty
cycles that meet the minimum on/off times. Figure 12 shows the
timing for a synchronization clock into the A8509 at 800 kHz.
The 150 ns minimum on-time and 150 ns minimum off-time are
900
800
700
C1
C3
I OUT
C4
t
Figure 11. Zoomed-in view of figure 9, showing quick shutdown when
FSET/SYNC shorted to ground, preventing IC running at very high
frequency; shows V OUT (ch1, 10 V/div.), V FSET/SYNC (ch2, 1 V/div.),
I IN (ch3, 2 A/div.), and I OUT (ch4, 1 A/div.), t = 10 μ s/div.
600
500
400
300
200
t PWSYNCON
150 ns
950 ns
7
9
11 13 15 17
FSET Resistor Value, R FSET (k Ω )
19
21
T = 1.25 μ s
150 ns
t PWSYNCOFF
Figure 9. Switching Frequency as determined by R FSET value.
Figure 12. SYNC pulse minimum on and off time
requirements, for an 800-kHz clock.
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
10
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