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| 型号： | A8698ELJTR-T |
| 厂商： | Allegro Microsystems Inc |
| 文件页数： | 9/12页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK ADJ 3A 8SOIC |
| 标准包装： | 1 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.8 V ~ 20 V |
| 输入电压： | 8 V ~ 25 V |
| PWM 型： | 电流模式 |
| 电流 - 输出： | 3A |
| 同步整流器： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm Width）裸露焊盘 |
| 包装： | 标准包装 |
| 供应商设备封装： | 8-SOIC-EP |
| 产品目录页面： | 1142 (CN2011-ZH PDF) |
| 其它名称： | 620-1177-6 |
A8698
Wide Input Voltage 3.0 A Step Down Regulator
the connection. The R r should be much larger than the feedback
resistor to prevent any potential offset in output voltage. For
example, if R f < 10 k Ω , R r should be 1 M Ω . C r should be selected
based on the following equation:
Note. The curve represents the minimum RTSET value. When
calculating R TSET , be sure to use V IN (max) / V OUT (min). Resistor
tolerance should also be considered, so that under no operating
C r (max) =
( V IN (min) – V FB ) × t ON (min)
0.05 × R r
(5)
conditions the resistance on the TSET pin is allowed to go below
the minimum value.
where Cr is in pF, t ON (min) is in μ s, and R r is in M Ω .
RTSET Selection. Correct selection of RTSET values will
ensure that minimum on-time of the switcher is not violated and
prevent the switcher from cycle skipping. For a given V IN to
V OUT ratio, the RTSET value must be greater than or equal to the
value defined by the curve in the plot below.
13.0
12.5
12.0
FB Resistor Selection. The impedance of the FB network
should be kept low to improve noise immunity. Large value resis-
tors can pick up noise generated by the inductor, which can affect
voltage regulation of the switcher.
11.5
11.0
10.5
10.0
Violation of
Minimum On-Time
um
n i i
lu
ET
R
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
M
m
Va
e
TS
of
Safe Operating Area
5.0
4.5
4.0
3.5
3.0
2.5
2.0
R TSET (k )
Allegro MicroSystems, LLC
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
9
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