参数资料
型号: ACE1202
厂商: Fairchild Semiconductor Corporation
英文描述: Arithmetic Controller Engine (ACEx⑩) for Low Power Applications
中文描述: 算术控制器引擎(ACEx⑩)的低功耗应用
文件页数: 27/39页
文件大小: 2121K
代理商: ACE1202
27
www.fairchildsemi.com
ACE1202 Product Family Rev. B.1
A
Figure 24: HBC signals for one byte message in PWM format
OCFLAG
SYNC
Period
"0"
ShiftCLK
Bit 7
DAT0
G2/G5
Output
IR/RF
CLOCK
Condition:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
"1"
"1"
"0"
"1"
"0"
"0"
"0"
START/STOP
TXBUSY
"0"
Figure 25: Sending series of encoded messages
OCFLAG
ShiftCLK
Bit 7
DAT0
G2/G5
Output
IR/RF
CLOCK
Conditions:
BPSEL = 0x12 [ "1", " 0 " = 3 * IR/RF Clocks]
DAT0 = 0x52 , 0x92
No. bit to encode = 8 (HBCNTRL = XXXX0111b)
START/STOP
TXBUSY
"1"
"1"
"0"
"1"
"0"
"0"
"0"
"1"
"0"
"1"
"0"
"0"
"0"
"0"
"1"
Software must set the START bit while OCFLAG is set in
order to send another message without introducing a delay.
STOP bit clear,
transmission ends.
"0"
SYNC
Period
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