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参数资料
| 型号： | ACE1202 |
| 厂商： | Fairchild Semiconductor Corporation |
| 英文描述： | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| 中文描述： | 算术控制器引擎（ACEx⑩）的低功耗应用 |
| 文件页数： | 29/39页 |
| 文件大小： | 2121K |
| 代理商： | ACE1202 |
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www.fairchildsemi.com
ACE1202 Product Family Rev. B.1
A
10.0 I/O Port
The eight I/O pins (six on 8-pin package option) are bi-directional
(see Figure 28) with the exception of G3 which is always an input
with weak pull-up. The bi-directional I/O pins can be individually
configured by software to operate as high-impedance inputs, as
inputs with weak pull-up, or as push-pull outputs. The operating
state is determined by the contents of the corresponding bits in the
data and configuration registers. Each bi-directional I/O pin can be
used for general purpose I/O, or in some cases, for a specific
alternate function determined by the on-chip hardware.
10.1 I/O registers
The I/O pins (G0-G7) have three memory-mapped port registers
associated with the I/O circuitry: a port configuration register
(PORTGC), a port data register (PORTGD), and a port input
register (PORTGP). PORTGC is used to configure the pins as
inputs or outputs. A pin may be configured as an input by writing
a 0 or as an output by writing a 1 to its corresponding PORTGC bit.
If a pin is configured as an output, its PORTGD bit represents the
state of the pin (1 = logic high, 0 = logic low). If the pin is configured
as an input, its PORTGD bit selects whether the pin is a weak pull-
up or a high-impedence input. Table 14 provides details of the port
configuration options. The port configuration and data registers
can both be read from or written to. Reading PORTGP returns the
value of the port pins regardless of how the pins are configured.
Since this device supports MIW, PORTG inputs have Schmitt
triggers.
Table 14: I/O configuration options
Configuration Bit
Data Bit
Port Pin Configuration
0
0
High-impedence input (TRI-STATE input)
0
1
Input with pull-up (weak one input)
1
0
Push-pull zero output
1
1
Push-pull one output
Figure 28: PORTG Logic Diagram
GXPULLEN
GXBUFEN
GXOUT
GXIN
PADGX
Figure 29: I/O Register bit assignments (PORTGC,PORTGD, PORTGD)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
13
G7
13
G6
G5
G4
14
G3
G2
G1
G0
13
Available only on the 14-pin package option
14
G3 is always an input with weak pull-up
相关PDF资料 |
PDF描述 |
|---|---|
| ACE12022 | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE12022B | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE1202BEM8X | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE12022EN14 | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE12022BEN14 | Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ACE12022 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE12022B | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE12022BE | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE12022BEM | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
| ACE12022BEM8 | 制造商:FAIRCHILD 制造商全称:Fairchild Semiconductor 功能描述:Arithmetic Controller Engine (ACEx⑩) for Low Power Applications |
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