参数资料
| 型号： | AD1852JRSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/20页 |
| 文件大小： | 0K |
| 描述： | IC DAC STEREO 24BIT 5V 28-SSOP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 47 |
| 位数： | 24 |
| 数据接口： | DSP，I²S，串行，SPI? |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 265mW |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 管件 |
| 输出数目和类型： | 4 电压，单极 |
| 采样率（每秒）： | 192k |
| 产品目录页面： | 781 (CN2011-ZH PDF) |
AD1852
Rev. A | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DGND 1
MCLK 2
CLATCH 3
CCLK 4
DVDD
28
SDATA
27
BCLK
26
LRCLK
25
CDATA 5
NC 6
192/48 7
RESET
24
MUTE
23
ZEROL
22
ZEROR 8
IDPM0
21
DEEMP 9
IDPM1
20
96/48 10
FILTB
19
AGND 11
AVDD
18
OUTR+ 12
OUTL+
17
OUTR– 13
OUTL–
16
FILTER 14
AGND
15
TOP VIEW
(Not to Scale)
AD1852
08
45
7-
00
2
Figure 2. Pin Configuration
Table 11. Pin Function Descriptions
Pin No.
Mnemonic
Input/Output
Description
1
DGND
I
Digital Ground.
2
MCLK
I
Master Clock Input. Connect to an external clock source running at either 256 fS, 384 fS, 512 fS,
768 fS, or 1024 fS.
3
CLATCH
I
Latch Input for SPI Control Data Port. This input is rising-edge sensitive.
4
CCLK
I
SPI Control Clock Input for Control Data. Control input data must be valid on the rising edge of
CCLK. CCLK may be continuous or gated.
5
CDATA
I
SPI Control Data Input, MSB First. SPI data port for controlling AD1852 functions as described in
the SPI Register Definitions section.
6
NC
No Connect.
7
192/48
I
192 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 192 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 11 of the control register.
8
ZEROR
O
Right Channel Zero Flag Output. This pin goes high when the right channel has no signal input
for more than 1024 LR clock cycles.
9
DEEMP
I
De-Emphasis. Digital de-emphasis is enabled when this input signal is high. This is used to
impose a 50 μs/15 μs response characteristic on the output audio spectrum at an assumed
44.1 kHz sample rate. Curves for 32 kHz and 48 kHz sample rates may be selected via the SPI
control register.
10
96/48
I
96 kHz/48 kHz Hardware Sample Rate Selection. When it is asserted high, this pin selects 96 kHz.
When it is asserted low, this pin selects 48 kHz. It is OR’d with Bit 10 of the control register.
11, 15
AGND
I
Analog Ground.
12
OUTR+
O
Right Channel Positive Line Level Analog Output.
13
OUTR
O
Right Channel Negative Line Level Analog Output.
14
FILTR
O
Voltage Reference Filter Capacitor Connection. Bypass and decouple the voltage reference
with parallel 10 μF and 0.1 μF capacitors to the AGND.
16
OUTL
O
Left Channel Negative Line Level Analog Output.
17
OUTL+
O
Left Channel Positive Line Level Analog Output.
18
AVDD
I
Analog Power Supply. Connect this pin to the analog 5 V supply.
19
FILTB
Filter Capacitor Connection. Connect 10 μF||10 nF capacitor to AGND (Pin 15).
20
IDPM1
I
Input Serial Data Port Mode Control One. With IDPM0, defines 1 of 4 serial modes.
21
IDPM0
I
Input Serial Data Port Mode Control Zero. With IDPM1, defines 1 of 4 serial modes.
22
ZEROL
O
Left Channel Zero Flag Output. This pin goes high when the left channel has no signal input
for more than 1024 LR clock cycles.
23
MUTE
I
Mute. Assert this pin high to mute both stereo analog outputs. De-assert low for normal operation.
24
RESET
I
Reset. The AD1852 is reset on the rising edge of this signal. The serial control port registers are
reset to the default values. For normal operation, assert this pin high.
相关PDF资料 |
PDF描述 |
|---|---|
| VI-B72-MY-F2 | CONVERTER MOD DC/DC 15V 50W |
| SN74AVCH4T245PWT | IC BUS TRANSCVR 4BIT 16TSSOP |
| VI-B71-MY-F2 | CONVERTER MOD DC/DC 12V 50W |
| VI-JNX-MZ-F4 | CONVERTER MOD DC/DC 5.2V 25W |
| VI-B70-MY-F2 | CONVERTER MOD DC/DC 5V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD1852JRSZ | 制造商:Analog Devices 功能描述:DAC 24BIT 192KHZ SIG DEL 28SSOP |
| AD1852JRSZRL | 功能描述:IC DAC STEREO 24BIT 28-SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD1853 | 制造商:AD 制造商全称:Analog Devices 功能描述:Stereo, 24-Bit, 192 kHz, Multibit DAC |
| AD1853JRS | 制造商:Analog Devices 功能描述:DAC 2-CH Delta-Sigma 24-bit 28-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:STEREO, 192KHZ MULTIBIT SIGMA DELTA DAC - Bulk 制造商:Analog Devices 功能描述:IC STEREO 24-BIT DAC |
发布紧急采购，3分钟左右您将得到回复。