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参数资料
| 型号： | AD1895AYRSZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC SAMP-RATEHP/CONV 24BIT 28SSOP |
| 标准包装： | 1,500 |
| 类型： | 采样率转换器 |
| 应用： | 车载音频，接收器，机顶盒 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 带卷 (TR) |
REV. B
AD1895
–20–
Serial Data Ports—Data Format
The Serial Data Input Port Mode is set by the logic levels on the
SMODE_IN_0/SMODE_IN_1/SMODE_IN_2 pins. The serial
data input port modes available are left justified, I
2S, and right
justified (RJ), 16, 18, 20, or 24 bits, as defined in Table I.
Table I. Serial Data Input Port Mode
SMODE_IN_[0:2]
21
0
00
0Left Justified
00
1
I
2S
01
0Undefined
01
1Undefined
10
0Right Justified, 16 Bits
10
1Right Justified, 18 Bits
11
0Right Justified, 20 Bits
11
1Right Justified, 24 Bits
The Serial Data Output Port Mode is set by the logic levels on the
SMODE_OUT_0/SMODE_OUT_1 and WLNGTH_OUT_0/
WLNGTH_OUT_1 pins. The serial mode can be changed to left
justified, I
2S, right justified, or TDM as defined in the Table II. The
output word width can be set by using the WLNGTH_OUT_0/
WLNGTH_OUT_1 pins as shown in
Table III. When the output word width is less than 24 bits, dither is
added to the truncated bits. The Right-Justified Serial Data Out
Mode assumes 64 SCLK_O cycles per frame, divided evenly
for left and right. The AD1895 also supports 16-bit, 32-clock
packed input and output serial data in LJ, RJ, and I
2S format.
Table II. Serial Data Output Port Mode
SMODE_OUT_[0:2]
10
Interface Format
00
Left Justified (LJ)
01
I
2S
10
TDM Mode
11
Right Justified (RJ)
Table III. Word Width
WLNGTH_OUT_[0:1]
10
Word Width
00
24 Bits
01
20 Bits
10
18 Bits
11
16 Bits
The following timing diagrams show the serial mode formats.
MSB
1/
f
s
TDM MODE – 16 BITS TO 24 BITS PER CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
MSB
LSB
MSB
LSB
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
LRCLK
SCLK
SDATA
NOTES
1. LRCLK NORMALLY OPERATES AT ASSOCIATIVE INPUT OR OUTPUT SAMPLE FREQUENCY (
f
s)
2. SCLK FREQUENCY IS NORMALLY 64
LRCLK EXCEPT FOR TDM MODE, WHICH IS N
64
f
s,
WHERE N = NUMBER OF STEREO CHANNELS IN THE TDM CHAIN. IN MASTER MODE, N = 4
MSB
I2S MODE – 16 BITS TO 24 BITS PER CHANNEL
RIGHT-JUSTIFIED MODE – SELECT NUMBER OF BITS PER CHANNEL
LEFT-JUSTIFIED MODE – 16 BITS TO 24 BITS PER CHANNEL
Figure 10. Input/Output Serial Data Formats
Interface Format
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