参数资料
型号: AD1939YSTZRL
厂商: Analog Devices Inc
文件页数: 17/32页
文件大小: 0K
描述: IC CODEC 24BIT ADC/DAC 64-LQFP
标准包装: 1,500
类型: 通用
数据接口: 串行
分辨率(位): 24 b
ADC / DAC 数量: 4 / 8
三角积分调变:
S/N 比,标准 ADC / DAC (db): 94 / 94
动态范围,标准 ADC / DAC (db): 105 / 110
电压 - 电源,模拟: 3 V ~ 3.6 V
电压 - 电源,数字: 3 V ~ 3.6 V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
AD1939
Data Sheet
Rev. E | Page 24 of 32
CONTROL REGISTERS
DEFINITIONS
The global address for the AD1939 is 0x04, shifted left one bit due to the R/W bit. All registers are reset to 0, except for the DAC volume
registers that are set to full volume.
Note that the first setting in each control register parameter is the default setting.
Table 14. Register Format
Global Address
R/W
Register Address
Data
Bit
23:17
16
15:8
7:0
Table 15. Register Addresses and Functions
Address
Function
0
PLL and Clock Control 0
1
PLL and Clock Control 1
2
DAC Control 0
3
DAC Control 1
4
DAC Control 2
5
DAC individual channel mutes
6
DAC L1 volume control
7
DAC R1 volume control
8
DAC L2 volume control
9
DAC R2 volume control
10
DAC L3 volume control
11
DAC R3 volume control
12
DAC L4 volume control
13
DAC R4 volume control
14
ADC Control 0
15
ADC Control 1
16
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit
Value
Function
Description
0
Normal operation
PLL power-down
1
Power-down
2:1
00
INPUT 256 (× 44.1 kHz or 48 kHz)
MCLKI/XI pin functionality (PLL active), master clock rate setting
01
INPUT 384 (× 44.1 kHz or 48 kHz)
10
INPUT 512 (× 44.1 kHz or 48 kHz)
11
INPUT 768 (× 44.1 kHz or 48 kHz)
4:3
00
XTAL oscillator enabled
MCLKO/XO pin, master clock rate setting
01
256 × fS VCO output
10
512 × fS VCO output
11
Off
6:5
00
MCLKI/XI
PLL input
01
DLRCLK
10
ALRCLK
11
Reserved
7
0
Disable: ADC and DAC idle
Internal master clock enable
1
Enable: ADC and DAC active
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