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参数资料
| 型号： | AD5011B |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP48 |
| 封装： | LQFP-48 |
| 文件页数： | 3/8页 |
| 文件大小： | 93K |
| 代理商： | AD5011B |
AD5011
–3–
REV PrA
PRELIMINARY TECHNICAL DATA
Parameter
AD7346B
Min
Units
T est Conditions/Comments
Typ
Max
LOGIC OUT PUT S
Output Logic High, V
OH9
Output Logic Low, V
OL
VDD - 0.3
V
V
I
OUT
= 200
m
A
I
OUT
= 200
m
A
0.3
POWER SUPPLIES
AVDD, DVDD
IDD
Normal Mode (excluding Driver)
Line Driver
3.15
3.3
3.45
V
32
75
mA
mA
33
W
Differential Load
1
Operating temperature range is as follows: B Version: –40°C to +85°C.
2
T he complete transmit path spectrum and pulse shape comply with ET SI requirements. SNR and T HD are measured within a 547 kHz bandwidth. Noise and Spurious
tones beyong 540 kHz are therefore excluded.
3
T he transmit DAC maximum update rate is half the maximum output data rate i.e. 1168 kHz. T he maximum transmit clock is 16 x 1168 = 18.688 MHz.
4
T here are three ranges (bottom range, mid range, top range), each range being divided into eight steps. T he transmit filter corner frequency can be set independently from
the receive filter corner frequency. the filter tuning circuit requires a continuous 16.384 MHz clock applied to the Fclk pin.
5
T ransformer turns ratio = 1:2:3 at 50 kHz when loaded by ET SI (RT R/T M3036) HDSL test loops.
6
With 547 kHz filter snd 0 dB PGA gain selected.
7
T he PGA gain is set by setting the PGA-GC bits in the control register.
8
T he input switching threshold voltage is approximately 1.2 V to allow interfacing to 2.5 V and 3.3 V logic.
9
T he output level is determined by the voltage on the logic supply pin V
DRIVE
.
Specifications subject to change without notice.
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