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参数资料
| 型号： | AD5011B |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP48 |
| 封装： | LQFP-48 |
| 文件页数： | 7/8页 |
| 文件大小： | 93K |
| 代理商： | AD5011B |
AD5011
–7–
REV PrA
PRELIMINARY TECHNICAL DATA
Control Register Functions
Mnemonic
Function
R /
W
When R/
W
is high, the register bank addressed by SEL[2:0] is loaded into the output shift register.
Serial data will subsequently be output onto the DR pin. If R/
W
is low, the serial input data located
at D[11:0] will be written into the register bank addressed by SEL[2:0].
When
PWDN-Tx
is low, the entire transmit channel is powered down. T he line driver output is
high impedance when the transmit channel is powered down.
When this bit is low, the entire receive channel is powered down.
When this bit is high, analog loopback is selected.
When this bit equals 1, the ADC buffer is bypassed.
When this bit equals 1, the receive filter is bypassed.
When T x-GAIN-SEL equals 1, the output of the transmit filter is attenuated by 6 dB.
T he transmit and receive programmable filter corner frequencies are addressed by the 11-bits words
T PFD and RPFD respectively. T PFD data is loaded from the serial input register to the transmit
filter register if SEL[2:0] = 010. RPFD data is written to the receive filter register if SEL[2:0] =
010. If WRBOT H equals 1 during either of the above conditions, the word in the serial input
register is loaded into both the T FPD and RFPD registers.
PWDN-Tx
PWDN-Rx
L OOPBAC K
AA-BU F -BP
AA-F L T R -BP
T x-G AIN-SE L
W R BOT H
T able 1. Control Register
Serial Register SE L [2:0]=000
SE L [2:0]=001
T x Prog Filt Reg
SE L [2:0]=010
Rx Prog Filt Reg
SE L [2:0]=011
T est Purposes Only
Control Reg
D [15]
D [14]
D [13]
D [12]
D [11]
D [10]
D [9]
D [8]
D [7]
D [6]
D [5]
D [4]
D [3]
D [2]
D [1]
D [0]
R/
W
= 0
SEL[2] = 0
SEL[1] = 0
SEL[0] = 0
PWDN-Tx
PWDN-Rx
L OOPBAC K
AA-BU F -BP
AA-F L T R -BP
T x-G AIN-SE L
T x-D A C OU T
T x-L PF -BP
T x-D R V R -BP
PG A-G C 2
PG A-G C 1
PG A-G C 0
R/
W
= 0
SEL[2] = 0
SEL[1] = 0
SEL[0] = 1
W R BOT H
T PF D [10]
T PF D [9]
T F PD [8]
T F PD [7]
T F PD [6]
T F PD [5]
T F PD [4]
T F PD [3]
T F PD [2]
T F PD [1]
T F PD [0]
R/
W
= 0
SEL[2] = 0
SEL[1] = 1
SEL[0] = 0
W R BOT H
R PF D [10]
R PF D [9]
R PF D [8]
R F PD [7]
R F PD [6]
R F PD [5]
R F PD [4]
R F PD [3]
R F PD [2]
R F PD [1]
R F PD [0]
R/
W
= 0
SEL[2] = 0
SEL[1] = 1
SEL[0] = 1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Configuring the T ransmit Channel
T x-D AC OU T
T x-F IL T -BP
T x-D RV R-BP
C onfiguration
0
1
0
0
0
0
Default. All Components in the T x channel are used.
T he DAC output is seen at the line driver output pins. T he line driver
amplifier output is in a high impedance state.
T he T x filter is bypassed. T he DACOUT is fed to the PGA. T he
filter amplifier output is in a high impedance state.
T he filter output is seen at the line driver output pins. T he line driver
amplifier output is in a high impedance state.
0
1
0
0
0
1
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