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参数资料
| 型号： | AD5011B |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 数字传输电路 |
| 英文描述： | 2 Pair/1 Pair ETSI Compatible HDSL Analog Front End |
| 中文描述： | DATACOM, DIGITAL SLIC, PQFP48 |
| 封装： | LQFP-48 |
| 文件页数： | 4/8页 |
| 文件大小： | 93K |
| 代理商： | AD5011B |
AD5011
–4–
REV PrA
PRELIMINARY TECHNICAL DATA
TIMNGCHARACTERISTICS
(V
DD
= +2.7 V to+5.5 V; AGND = DGND = 0 V, unless otherwse noted)
Limit at
T
MIN
to T
MAX
Parameter
(B Version)
Units
T est C onditions/C omments
ADC C L K <= 1160kHz
t
1
1.5*t
3
2*t
3
2.5*t
3
3*t
3
26.939
5
10
ns min
ns typ
ns min
ns typ
ns min
ns min
ns min
ADCCL K Rising Edge to SCL K Rising Edge Delay
t
2
SCL K Rising Edge to ADCCL K Falling Edge Delay
t
3
t
4
t
5
SC L K Period (1/32*ADC C L K Period)
Data Setup T ime Before SCL K Falling Edge
Data Hold T ime After SCL K Falling Edge
1160 kHz < ADCCLK <= 2320 kHz
t
6
20
1*t
8
t
7
1.5*t8
2*t
8
t
8
26.939
t
9
5
t
10
10
ns min
ns typ
ns min
ns typ
ns min
ns min
ns min
ADCCL K Rising Edge to SCL K Rising Edge Delay
SCL K Rising Edge to ADCCL K Falling Edge Delay
SC L K Period (1/16*ADC C L K Period)
Data Setup T ime Before SCL K Falling Edge
Data Hold T ime After SCL K Falling Edge
T RANSMIT D AC
t
11
t
12
t
13
t
14
t
15
53.5
12
10
t
11
3
ns min
ns min
ns min
ns min
ns min
t11/2
T xC L K Period (1/18.688 MHz)
Data Setup T ime Before T xCL K Rising Edge
Data Hold T ime After T xCLK Rising Edge
T xSY NC L ow T ime
T xCL K Rising Edge to T xSY NC Falling Edge Delay
ns max
C ONT ROL RE G IST E R
t
16
50
76
15
t
16
- 15
15
t
16
- 15
t
16
7
10
7
10
ns min
ns typ
ns min
ns max
ns min
ns max
ns typ
ns min
ns min
ns min
ns min
SPIC L K Period
t
17
T FS Setup T ime Before SPICL K Falling Edge
t
18
T FS Hold T ime After SPICL K Falling Edge
t
19
t
20
t
21
t
22
t
23
T FS High T ime
DT Setup T ime Before SPICL K Falling Edge
DT Hold T ime After SPICL K Falling Edge
DR Setup T ime Before SPICLK Falling Edge (R/
W
= 1)
DR Hold T ime After SPICLK Falling Edge (R/
W
= 1)
Guaranteed by design but not production tested.
D11
D10
D1
D0
ADCCLK
t
1
t
5
D11
D10
D9
SCLK
SDO
t
2
t
3
t
4
Figure 1. ADC Timing (ADCCLK <= 1160 kHz)
SCLK activity and serial output data activity does not coincide with the sesitive ADCCLK clock edges
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